The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.
Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG. The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.). There is no election of a Young Professional this year.
The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.
EPS Major Awards
A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:
The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.
Nomination Period September 8, 2021 - January 26, 2022
Title: Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications
Date: September 30, 2021
Time: 12:00 pm PDT/3:00 pm EDT
Presenter: Pragya Shrestha, NIST
You can earn 1 Professional Development Hour (PDH) for attending this webinar by completing the PDH survey form
Abstract: Cryogenic electronics have a wide range of applications, ranging from quantum information science to extra-terrestrial electronics to gravitational wave research to high performance computing. However, the dominant application leading the way for cryogenic electronics research, is quantum computing where electronic functionality at the 4 K or below has become a requirement. The most promising candidate to fulfil this functionality without disturbing the cryogenic environment with a path to large-scale integration is CMOS. Therefore, a lot of effort has been put in to hunt for the right CMOS device technology and obtain their low temperature models for designing reliable and accurate cryogenic circuits. Though it has been acknowledged that precise characterization is crucial for reliable low power and low temperature circuit design, obtaining reliable device characterization and reliability at low temperatures has not been sufficiently addressed. Absent specially is the time domain characterization of devices which are crucial for designing accurate analog circuitry. This webinar will review the challenges of using cryogenic CMOS in the field of quantum computing and further discuss the motivation for creating cryogenic ultra-fast time domain device characterization setup for accurate high-performance cryogenic CMOS circuit design.
Date: November 11-12, 2021 (virtual, and in-person in Silicon Valley)
Location: Silicon Valley, CA, USA
Abstract due date: September 30th 2021.
Proposals for presentations as an abstract in the fields of Reliability for Electronic and Photonic Packaging are solicited under the technical areas highlighted in thislink<https://attend.
This symposium will focus on quantified reliability, accelerated testing and probabilistic assessments in electronics and photonics packaging. This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses.
COVID-19 : Due to the evolving nature of the pandemic, the symposium is being planned as a hybrid event, with both in‐person and WebEx participation .
REPP Symposium Committee
The 23rd IEEE Electronics Packaging Technology Conference (EPTC2021) is an international event organized by the IEEE RS/EPS/EDS Singapore Chapter and co-sponsored by IEEE Electronics Packaging Society (EPS). It aims to provide a platform for the dissemination of innovations and new developments in semiconductor packaging and component technology, from design to manufacturing. Since its inauguration in 1997, EPTC has been established as a highly reputed electronics packaging conference and is the EPS flagship conference in the Asia-Pacific Region 10. It covers diverse areas of electronics packaging technology including modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G, autonomous vehicles, photonics, emerging technologies, 2.5D/3D integration, and smart manufacturing. EPTC2021 features keynotes, technology talks, invited presentations, technical presentations, sponsorship & exhibition corners, and virtual networking activities.
Submit your abstract for the 72nd ECTC!
The premier international packaging, components, and
microelectronics systems technology conference
You are invited to submit an abstract proposal about new
developments and technology related to the following:
21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm 2022)
Sponsored by IEEE EPS
Co-located with the 72nd ECTC 2022 – Joint registrations available at discounted rate
When: May 31 – June 3, 2022
Where: Sheraton Hotel & Marina San Diego, CA USA
ITherm 2022 is an international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems. In addition to paper presentations and vendor exhibits, ITherm 2022 will have keynote lectures by prominent speakers, panel discussions, invited Tech Talks, professional development courses and several student design competitions.
All papers will be peer reviewed and published in the ITherm proceedings on IEEE Xplore. Student first authors will have the opportunity to apply for ITherm travel grants in order to make an oral presentation and participate in a Student Poster and Networking Session.
Rohit Sharma1, Jose E. Schutt-Aine2, Wiren Dale Becker3
1 Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, INDIA
2 Department of Electrical and Computer Engineering. University of Illinois Urbana-Champaign Urbana, IL 61801, USA
3 IBM, Poughkeepsie, NY, USA
In this paper, we present an overview of the electrical-thermal co-design and co-analysis of 3D ICs in heterogeneously integrated systems. We present the generalized framework for electrical-thermal co-design. The application of electrical-thermal co-design and co-analysis as applied to chiplets is addressed.
On Saturday, August 21, free from the hustle and bustle of the workweek, it was a day of relaxation. The smoke that had blanketed the sky around Silicon Valley had cleared up just in time for our EPS SCV Chapter summer barbeque. Indeed, Paul and Gail Wesling’s pool glimmered welcomingly as we basked in the California sun. But it lay largely ignored (except for several of our children) as the current and past ExCom officers of the Santa Clara Valley EPS Chapter happily met up after a long pandemic-caused absence.