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The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

·       Outstanding Sustained Technical Contribution Award

·       Electronics Manufacturing Technology Award

·       William Chen Distinguished Service Award

·       Exceptional Technical Achievment Award

·       Outstanding Young Engineer Award

·       Regional Contributions Award


The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Awards Nomination Form

PhD Fellowship Nomination Form 

Nomination Period September 15, 2023 - January 21, 2024

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Election Principles

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members-at-Large will be selected each year to represent the regional composition of the Society membership and one Member-at-Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect Members-at-Large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.).  

Round 2 of the EPS Distinguished Achievement Certificates nomination period is now open.

Applications for these certificates will be accepted until October 31, 2023:

Distinguished Achievement Certificate for Professional Engagement and Service

Distinguished Achievement Certificate for Technical Leadership and Expertise 

Nomination Form

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Title: Future Product and Platform Resiliency Panel Discussion: “What design, architecture and Test features and best practices do we need to guarantee zero  failures over the customer's platform for a trillion trillion transistor product?"

Date: 19 September, 2023

Time: 7:00am - 8:00am  PDT

Panelists Jyotika Athavale, Synopsys; Adam Cron, Synopsys; Teresa McLaurin, ARM; Saket Goyal, Broadcom


Register here

The 9th International IEEE Conference on Microwaves, Communications, Antennas, Biomedical Engineering and Electronic Systems (COMCAS 2023) will be held 6-8 November, 2023 in Tel Aviv, Israel.

COMCAS will continue to evolve and provide an advanced multidisciplinary forum for the exchange of ideas, research results, and industry experience in a range of key areas i.e., microwaves, communications and sensors, antennas, biomedical engineering, RF and microwave devices and circuits, thermal management and electronic packaging, signal processing and imaging, as well as radar, acoustics and microwave system engineering. In its entirety the event includes a technical program, industry exhibits, and guest presentations from global experts on recent academic and industry advancements.

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Submit your abstract for the 74th ECTC!

The premier international packaging, components, and microelectronics systems technology conference 

Submission Guidelines

The content must be original, previously unpublished, non-confidential and without commercial content.

All abstracts and proposals must be submitted electronically at our website by 09 October 2023. Selected authors and instructors will be announced by 15 December 2023. The first 100 people to submit abstracts will be entered into a drawing to win a free ECTC 2023 registration.

ECTC 2024 will be held May 28 - 31, 2024 at the Gaylord Rockies Resort & Convention Center, Colorado.

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Erasenthiran Poonjolai1, Pradeep Jayavelmurugan2, Emre Armagan3, Sandeep Mallampati4, Bjorn Birkner5, Carmine Pagano2, Bhavanasri Devaraj3, Vidya Jayaram1, Benjamin Esposito2, John Sotir2, Saikumar Jayaraman1, Darren Crum6

1Technology Integration, Assembly Test Technology Development, Intel Corp

2SHIP Business / Embedded Acceleration Division, PSG Intel Corp

3Quality and Reliability , Assembly Test Technology Development, Intel Corp

4Product Reliability Qualification Group

5Sort Test Technology Development, Intel Corp

6Naval Surface Warfare Center (NSWC), Crane Division


Abstract -  Heterogeneous integration using Multi chip packaging has become a key technology enabler for meeting the high bandwidth demands of next generation compute architectures. Recent advances in packaging technologies, such as Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology have enabled building complex compute architectures in a single package using multi-technology chiplet integration. These advances have provided designers with the flexibility to build systems in a single package using optimized and custom chiplets with unique functionalities and process technology of choice coupled with standardized low power, high bandwidth IO links. Intel's Advanced Interface Bus (AIB) is a die-to-die PHY level standard that enables a modular approach to system design with a library of chiplet intellectual property (IP) blocks. Combining Intel’s FPGAs with AIB interfaces and EMIB packaging technology provides a unique opportunity to develop a new class of products for defense applications that meets the system requirements in a small form factor with greater flexibility, scalability, ease of use, and faster time to market. 

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Tetsu Tanaka1, Takafumi Fukushima1, Christof Landesberger2, Peter Ramm2

1Tohoku University, 2Fraunhofer EMFT 

E-mail: Aanaka@lbc.mech.tohoku.ac.jp; christof.landesberger@emH.fraunhofer.de


Flexible Hybrid Electronics

In recent years, wearable devices, implantable devices, and the Internet of Things have become increasingly popular as such devices have become smaller and lighter, and the development of wireless communications has made it easier for device-to-device connection, thus diversifying the applications of electronic devices. Although conventional devices are limited by the shape of their internal printed circuit boards (PCBs), making them impossible to bend, lots of flexible devices based on organic semiconductors and thin film transistors (TFT) [1] using flexible substrates instead of rigid PCBs have been reported. However, there are several issues with conventional flexible devices using organic semiconductors. First, carrier mobility of organic semiconductors’ is lower than inorganic single-crystal semiconductors such as Si. Since carrier mobility is an important factor in determining the operation speed and power consumption of an IC, it is challenging to construct high-performance devices with organic semiconductors compared to those with inorganic single-crystal semiconductors. The second problem is the difficulty of manufacturing high-density wiring. The wiring width of typical printed electronics is several millimeters to several tens of micrometers, making it challenging to achieve highly integrated and high-performance flexible devices.

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                                                      Rinaldo Miorini                                                              Dana Teague

                                                       GE Research                                                    Air Force Research Laboratory

                                          rinaldo.miorini.phd.us@ieee.org                                       joseph.teague@us.af.mil



High-power industrial lasers (such as those used in heavy industry and construction) present a brutally difficult thermal management challenge for a variety of reasons. The high-power diodes required for their function combine high heat fluxes (> 1 kW cm-2), with a very high isothermality (} 2 ℃ is the generally accepted value), at a relatively low temperature (23 ℃is used as a standard value) [1-5]. The heat generated by the system must ultimately be rejected to environments across a broad temperature range depending on where the laser is operated and employed. In addition to all this, thermal interfaces must be thermal-expansion matched to avoid deforming the laser diodes, which limits the available materials for construction. Traditionally, lasers have been developed and tested in laboratories, i.e., in a temperature-controlled environment, with access to large quantities of facility coolant. However, if one wanted to create a more integrated solution that could be transported and used in the field, the size, weight, power, and cooling constraints of this laboratory/facility would be unacceptable. The location in which the laser is used may not have tight temperature regulation, nor large coolant reservoirs available, nor the space needed for the necessary pumps, pipes, and control valves. 

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One-day Seminar on ANSYS CAE Solution:  Paving the way for future semiconductor technology advancement.

Reported by KS Siow

Kuala Lumpur's MIMOS Berhad was alive with excitement on August 23rd as it hosted the highly anticipated MIMOS High Value Semiconductor Technology Seminar, focusing on the utilization of ANSYS software. With a diverse mix of 70 participants representing universities and companies, the event highlighted the versatile applications of the finite element software ANSYS. The full-day event was organized by MIMOS and co-organized by CAD-IT (Ansys representative in Malaysia), Ansys, and IEEE Electronics Packaging Society (Malaysia).

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