Members Only: 3DIC Wokshop (Dec 2011)

General Chair: Lawrence Williams, ANSYS Corporation

 

       (Click on title to view presentation)

• Opportunities and Challenges for 3D Integrated Heterogeneous Electronic Systems, Prof. Muhannad Bakir, Integrated 3D Systems Group, Georgia Tech, Atlanta, GA
• Economics to Drive 3D Stacking, Dr. Phil Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, NC
• Stack Silicon Interconnect Development and Key Role of Supply Chain Collaboration, Dr. Suresh Ramalingam, Sr. Director, Xilinx, San Jose, CA
• Emerging Challenges for Power, Signal, and Reliability Verification on 3D-IC/Silicon Interposer Designs, Dr. Norman Chang, Co-Founder, Apache Design Systems, Ansys, San Jose, CA
• 3D IC Test Challenges and Solutions, Dr. Stephen Pateras, Product Marketing Director, Silicon Test, Mentor Graphics, San Jose, CA
• 3D Integration Challenges nd Progress: From TSV to Stacked Die Technologies, A. La Manna, K. Rebibis, Dr. Eric Beyne, Dr. B. Swinnen, IMEC, Leuven, Belgium
• Cost-Effective 3D Semiconductor Packaging Solutions Based on Embedded Die in Laminate Technology, Ted Tessier, SenthilSivaswamy, Flip Chip International LLC, Phoenix, AZ, Dr. Kazuhisa Itoi, Fujikura Ltd, Tokyo, Japan
• Challenges and Solutions in Mid-end and Back-end Processes for 2.5D and 3D TSV –an OSAT Perspective, Dr. Yeong Lee, Product and Tech. Marketing Director, STATS ChipPAC, Fremont, CA
• Advanced Underfillsfor 2.5D and 3D Applications, Dr. Rose Guino, Dr. Betty Huang, Dr. Kevin Becker, Dr. T. Takano, Henkel Electronic Materials, LLC, Irvine, CA
• 3D TSV Interposer and its Applications, Dr. GS Kim, Founder & CEO, EPWorks, Ltd. Seoul, Korea
• Via Reveal –High rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing, David Butler, Vice President –Marketing, SPTS Technologies, Newport, UK