Members Only: Thin is In (July 2012)
Material provided here is for viewing by IEEE EPS Members ONLY. Please do not redistribute. |
Tuesday, July 10, 2012 at SEMICON West 2012
Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. Here, thin 3D-packaging is one of the key Technologies to achieve these goals. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.
In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on the readiness for commercialization and what the future directions and opportunities in this emerging area of “Thin Packaging Technology.
Session Co-chairs:
Rolf Aschenbrenner, Fraunhofer IZM, Berlin and Jie Xue, Cisco
(Click on title to view presentation)
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Thin is In: Packaging for Mobile Applications, Steve Bezuk, Qualcomm CDMA Technologies
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The Thin Package Challenge Never Ends, Bernd Appelt, ASE Group
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ChipletTTM and ChipsetTTM: A Fine Line Multilayer Flex Based Embedded Die Semiconductor Packaging Solution, Ted Tessier, Flip Chip International LLC
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eWLBTM Wafer-level Fan-out Technology – A New Package Platform for High Performance and Small Form Factor Packaging, Rajendra D. Pendse, STATSChipPAC, Inc.(this presentation is not available)
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Coreless Substrate. Its Performance and Future Direction, Mitsuharu Shimizu, Shinko
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Amkor's Thru Molded Via (TMV) Thin Package on Package Technology Roadmap, Robert Lanzone, Amkor Technology
Members Only: 3DIC Wokshop (Dec 2011)
Material provided here is for viewing by IEEE EPS Members ONLY. Please do not redistribute. |
CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA
General Chair: Lawrence Williams, ANSYS Corporation
(Click on title to view presentation)
- Opportunities and Challenges for 3D Integrated Heterogeneous Electronic Systems, Prof. Muhannad Bakir, Integrated 3D Systems Group, Georgia Tech, Atlanta, GA
- Economics to Drive 3D Stacking, Dr. Phil Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, NC
- Stack Silicon Interconnect Development and Key Role of Supply Chain Collaboration, Dr. Suresh Ramalingam, Sr. Director, Xilinx, San Jose, CA
- Emerging Challenges for Power, Signal, and Reliability Verification on 3D-IC/Silicon Interposer Designs, Dr. Norman Chang, Co-Founder, Apache Design Systems, Ansys, San Jose, CA
- 3D IC Test Challenges and Solutions, Dr. Stephen Pateras, Product Marketing Director, Silicon Test, Mentor Graphics, San Jose, CA
- 3D Integration Challenges nd Progress: From TSV to Stacked Die Technologies, A. La Manna, K. Rebibis, Dr. Eric Beyne, Dr. B. Swinnen, IMEC, Leuven, Belgium
- Cost-Effective 3D Semiconductor Packaging Solutions Based on Embedded Die in Laminate Technology, Ted Tessier, SenthilSivaswamy, Flip Chip International LLC, Phoenix, AZ, Dr. Kazuhisa Itoi, Fujikura Ltd, Tokyo, Japan
- Challenges and Solutions in Mid-end and Back-end Processes for 2.5D and 3D TSV –an OSAT Perspective, Dr. Yeong Lee, Product and Tech. Marketing Director, STATS ChipPAC, Fremont, CA
- Advanced Underfillsfor 2.5D and 3D Applications, Dr. Rose Guino, Dr. Betty Huang, Dr. Kevin Becker, Dr. T. Takano, Henkel Electronic Materials, LLC, Irvine, CA
- 3D TSV Interposer and its Applications, Dr. GS Kim, Founder & CEO, EPWorks, Ltd. Seoul, Korea
- Via Reveal –High rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing, David Butler, Vice President –Marketing, SPTS Technologies, Newport, UK
Members Only: What Makes Good Innovations into Great IP? (IMPACT 2013)
Material provided here is for viewing by IEEE EPS Members ONLY. Please do not redistribute. |
What Makes Good Innovations into Great IP?
IMPACT 2013 Session -- jointly organized by IEEE EPS and Perkins Coie LLP
October 23, 2013
Co-Chairs : Professor Kwang-Lung Lin (National Cheng Kung University, Taiwan)
Professor Kuo-Ning Chiang (National Tsing Hua University, Taiwan)
This session addressed the question of "What makes Good Innovations into Great IPs?" by a panel of experts from ITRI-Taiwan and United States. The presentation first looked at main features in patent systems similar to or based on the European patent system such as the Taiwan patent system and the unique features in the U.S. patent system. It also discussed the recent trends in patent enforcement and patent procurement in the U.S. electronics product market. In particular, the discussion used some litigation cases to illustrate processes and impacts of patent litigation before the U.S. federal courts and before the U.S. International Trade Commission (Section 337 investigation). As part of the strategy for patent litigation defenses and other patent disputes, the session covered the new U.S. post-grant proceedings for challenging validity of patents before the U.S. Patent Office. The final part of this session was a lively discussions with the panel and Q&As with the audience on IP issues for companies and institutions in Taiwan and Asia when selling products or commercializing their technologies in U.S.
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View Panelists (25 KB)
Members Only: Thin is In (July 2013)
Material provided here is for viewing by IEEE EPS Members ONLY. Please do not redistribute. |
Tuesday, July 9, 2013 at SEMICON West 2013
Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. One of the key technologies to achieve these goals is thin 3D-packaging. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.
In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on what the future directions and emerging opportunities in the “Thin Packaging Technology” area will be and their readiness for commercialization.
Session Co-chairs:
Rolf Aschenbrenner, Fraunhofer IZM, Berlin and Jie Xue, Cisco
(Click on title to view presentation)
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Packaging Technology Challenges for Mobile Computing Electronics (PDF 3135K) Mostafa Aghazadeh, Intel Corporation
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Challenges for Thin Memory Packaging Technology (PDF 1793K) Woong-Sun Lee, Ph.D., S.K. Hynix
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TSV/3DI Future (PDF 556K) Aron Lunde, Micron Technology
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The Large and Thin Flip Chip SUBSTRATE (PDF 778K) Koichi Nonomura, Kyocera
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Performance of Embedded Packages Drives Thin is In (PDF 217K) Johannes Stahr, AT&S
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Thin Module Technologies (PDF 2503K) Ou Li, ASE Group
Webinar: Power Electronics Packaging, Reliability, and Thermal Management
View Presentation File (PDF 3.43 MB)
Power Electronics Packaging, Reliability, and Thermal Management
Date/Time: 24 July 2014 8 a.m. PST, 11 a.m. EST (US)/ 4 p.m. GMT (Europe)/ 12 a.m. (Hong Kong) Duration: One hour Presenters: F. Patrick McCluskey (CALCE, University of Maryland, USA) Abstract: Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, and smart grids. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics. Following a review of heat transfer principles and thermal management techniques, along with physics-of-failure approaches to assess and ensure reliability, this short course will present the latest developments in the packaging, assembly, and thermal management of power electronic modules and systems, along with modeling and testing techniques. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components. |