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IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for
Innovative Mobile Devices

Tuesday, July 10, 2012 at SEMICON West 2012

Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. Here, thin 3D-packaging is one of the key Technologies to achieve these goals. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on the readiness for commercialization and what the future directions and opportunities in this emerging area of “Thin Packaging Technology.

Session Co-chairs:

Rolf Aschenbrenner, Fraunhofer IZM, Berlin and  Jie Xue, Cisco

 

(Click on title to view presentation)

  • eWLBTM Wafer-level Fan-out Technology – A New Package Platform for High Performance and Small Form Factor Packaging, Rajendra D. Pendse, STATSChipPAC, Inc.(this presentation is not available)

 

 

 

Material provided here is for viewing by IEEE EPS Members ONLY.  Please do not redistribute.
 
3D Integrated Circuits: Technologies Enabling the Revolution

CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA

 

General Chair: Lawrence Williams, ANSYS Corporation

 

       (Click on title to view presentation)

 

Material provided here is for viewing by IEEE EPS Members ONLY.  Please do not redistribute.

What Makes Good Innovations into Great IP?

 

IMPACT 2013 Session -- jointly organized by IEEE EPS and Perkins Coie LLP

October 23, 2013

Co-Chairs : Professor Kwang-Lung Lin (National Cheng Kung University, Taiwan)

                 Professor Kuo-Ning Chiang (National Tsing Hua University, Taiwan)

This session addressed the question of "What makes Good Innovations into Great IPs?" by a panel of experts from ITRI-Taiwan and United States.  The presentation first looked at main features in patent systems similar to or based on the European patent system such as the Taiwan patent system and the unique features in the U.S. patent system.  It also discussed the recent trends in patent enforcement and patent procurement in the U.S. electronics product market.  In particular, the discussion used some litigation cases to illustrate processes and impacts of patent litigation before the U.S. federal courts and before the U.S. International Trade Commission (Section 337 investigation).  As part of the strategy for patent litigation defenses and other patent disputes, the session covered the new U.S. post-grant proceedings for challenging validity of patents before the U.S. Patent Office.  The final part of this session was a lively discussions with the panel and Q&As with the audience on IP issues for companies and institutions in Taiwan and Asia when selling products or commercializing their technologies in U.S.


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   Material provided here is for viewing by IEEE EPS Members ONLY.  Please do not redistribute.       
IEEE/CPMT Workshop in: Thin Is In:
Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era

Tuesday, July 9, 2013 at SEMICON West 2013

Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. One of the key technologies to achieve these goals is thin 3D-packaging. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on what the future directions and emerging opportunities in the “Thin Packaging Technology” area will be and their readiness for commercialization.

Session Co-chairs:

Rolf Aschenbrenner, Fraunhofer IZM, Berlin and  Jie Xue, Cisco

 

(Click on title to view presentation)

 

 

View Presentation File  (PDF 3.43 MB)

 


Power Electronics Packaging, Reliability, and Thermal Management

 

Date/Time: 24 July 2014  8 a.m. PST, 11 a.m. EST (US)/ 4 p.m. GMT (Europe)/ 12 a.m. (Hong Kong)

Duration: One hour

Presenters: F. Patrick McCluskey (CALCE, University of Maryland, USA)

Abstract:  Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, and smart grids. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics.

Following a review of heat transfer principles and thermal management techniques, along with physics-of-failure approaches to assess and ensure reliability, this short course will present the latest developments in the packaging, assembly, and thermal management of power electronic modules and systems, along with modeling and testing techniques. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components.