Chiplet Definition

The naming of new technologies can be difficult and often inaccurate.  Over time, standards are developed and language becomes aligned. 

The cost of leading-edge nodes, combined with the lack of scaling of significant design blocks (ex:  analog) and die sizes reaching reticle size, is driving disaggregation (splitting up) of chip functions into their best price/performance nodes requiring new technologies to interconnect these functions.  

We are voicing our support in naming these small IP blocks “chiplets”.  It is not a perfect name but fits into our vernacular well and is gaining acceptance in our industry.  Our definition of “chiplet”, and what it is not, follows.  

We appreciate your inputs. 

David McCann

VP EPS Technology


Chiplet is not a package type, it is part of a packaging architecture. It is an integrated circuit block that has been specifically designed to communicate with other, similar chiplets, to form larger more complex ICs. Thus, in large and complex chip designs the design is subdivided into functional circuit blocks, often reusable IP blocks, called "chiplets", that are manufactured and recombined on high density interconnect.

Historically the need for multiple chips to deliver a specific function was driven by the reticle limit which dictated the maximum size of a chip possible to be fabricated. Designs that exceeded the reticle limit were split up into smaller dies to be manufacturable. As technology continued to enable increased integration, multiple dies were merged into single, more complex ICs. Thus, the origin of the term “system” on a chip or SoC.

More recently, economics has caused a reversal of that trend. As the industry moves to smaller process nodes, costs for yielding large dies increases. The desire to move to a chiplet-based design has been driven by the increasing cost of manufacturing devices on leading-edge process nodes. Compared to a 250 mm² die fabricated on a 45nm process, a 16nm process more than doubles the cost/mm² and a 7nm process further doubles that to 4x the cost per yielded mm². Moving to the 5 nm and even 3 nm nodes, is expected to make this even worse.                                                                                                     

The chiplet solution can be used to ease the economics of manufacturing such chips, with large numbers of transistors, at state-of-the-art nodes. In chiplet-based design the chip is broken down, by function, into multiple smaller chiplets and only the chiplets that require the latest node are made in that node.

Some envision, that in time, the greater use of chiplets will drive the package to become the new SoC, and chiplets become the new "IP". However, for this to be viable across packaging companies, there must be standard/common communication interfaces between chiplets. There are several solutions today, but standards must be chosen.

HIR logo

 2021 HIR Symposium

2019 Edition

Become a contributing member of the HI Roadmap

View HI Roadmap Presentations

View ITRS 2.0 2015 Edition

Next Phase of Innovation: Heterogeneous Integration

EE Times Article on Heterogeneous Integration Roadmap

Press Release:  EPS Honors Heterogeneous Integration Pioneer and Other Innovators

Following SIA's closure of ITRS activities in 2015, the Heterogeneous Integration Roadmap activities will continue -- sponsored by the IEEE Electronics Packaging Society (EPS), SEMI, IEEE Electron Devices Society (EDS), IEEE Photonics Society and the ASME EPPD Division, with the intention of expanding the roadmap collaboration to other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.

Global Advisory Council


The ITRS Assembly and Packaging Working Group has had many years of history of collaboration with the IEEE Societies in holding workshops and work sessions at IEEE Societies sponsored conferences and events around the world.  The basis of this collaboration is the common shared interest in a Technology Roadmap for the IEEE Societies’ membership, conference attendees and participants in the ITRS Technical Working Group work sessions.  IEEE Societies Conferences are high profile forums on the latest research and development in Packaging, Interconnect, Test and the materials, processes and equipment supporting this R&D. The Roadmap workshops of the ITRS had provided an opportunity for the participants to review the directions of these technologies and build a technology Roadmap looking 15 years into the future.

The collaboration in technical working groups (TWGs) that produced the ITRS Roadmap has continued with the establishment of the Heterogeneous Integration Focus Team in 2014. In 2015, a MOU was signed between the Heterogeneous Integration Focus Team and the IEEE EPS with the approval of the Semiconductor Industry Association (SIA) to ensure the collaboration was sustainable.

In the winter of 2015, SIA announced that it would bring the ITRS activities to a close with the publication of the 2015 Edition in the spring of 2016.

We believe that it is important to continue this Heterogeneous Integration Roadmap function for the profession, industry and the entire technical community. In the era of IoT, the Cloud, smart phones and intelligent automobiles, there is immense need for a pre-competitive technology roadmap providing a long term vision to the future and identifying difficult challenges and potential solutions. 

IEEE communities, including the IEEE Societies and Councils, are rich in creativity, innovation and knowledge across science, technology and arts associated with electronics. Bringing this mission under the auspices of the IEEE Technical Societies will fill this important need with the deep knowledge base from the Societies’ global membership and worldwide network. It would be a service to the global technical professionals and technical community consistent with the IEEE mission.  The goal for this roadmap is to be open and transparent. IEEE EPS provides institutional sponsorship to ensure sustainability and quality.

The Heterogeneous Integration Roadmap activities are sponsored by IEEE Electronics Packaging Society (EPS), SEMI,  IEEE Electron Devices Society (EDS),  IEEE Photonics Society and the ASME EPPD Division with the intention of expanding the roadmap collaboration to other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.  A document with definition of the mission, purpose, structure and governance for this Heterogeneous Integration Roadmap program was prepared and approved.

top of page


Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly (SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub-system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level performance and cost of ownership.

The mission of this Heterogeneous Integration Roadmap is to provide guidance to the profession, industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics. That progress is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the requirements for heterogeneous integration in the electronics industry through 2034, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

top of page


  • The Roadmap serves as a guideline for the global electronics industry of projected technology needs and opportunities for innovation.

  • The Roadmap is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment.

Serving the Profession, Industry, Academia and Research Institutes, the Roadmap provides:

  • A forecast of industry requirements to maintain the pace of progress for the industry and user community  over the next 15 years, and the next 25 years for the heterogeneous integration of emerging devices and materials which require a longer research development horizon.

  • Identification of difficult challenges that must be addressed to meet these industry requirements.

  • Where possible the Roadmap will identify research requirements and potential technical solutions.

top of page


  • An International Roadmap Committee (IRC) has been established by the sponsoring organizations, under the oversight of the EPS Society.

  • The IRC will initially be a group of ~6 people with representation from EPS, EDS, Photonics, SEMI, ASME EPPD and other IEEE and non-IEEE collaborating organizations, government and academia.

  • The Chair of the IRC will be named by the EPS President.

  • The Co-Chair of the IRC will be chosen by vote from the IRC.

  • The IRC will meet at least quarterly and publish minutes of the meetings.

  • The IRC will determine the Technical Working Groups (TWGs) that will be established to develop chapters of the Roadmap, appoint the TWG Chairs and approve the mission and scope statements of each Roadmap chapter.

  • TWG chairs will be responsible for recruiting the appropriate volunteers to address the scope of their Roadmap chapters.

  • The Roadmap will participate in the same peer review and quality control procedures as other IEEE publications.

  • The schedule and location of meetings at Society Conferences will be determined by the IRC for:
    • In person meetings of the full Roadmap membership
    • On-line meetings for all TWG Chairs
  • TWG Chairs will schedule in person meetings and on-line meetings for their members working sessions and share their schedule with the IRC.

  • The IRC will determine the schedule for preparation and publication of the Roadmap.

  • The Current members of the International Roadmap Committee are: Bill Chen, Chair ; Bill Bottoms (IEEE EPS); Tom Salmon (SEMI), Subramanian Iyer (IEEE EDS), Amr Helmy (IEEE Photonics Society) and Ravi Mahajan (ASME EPPD Division). Gamal Refai-Ahmed is the ASME EPPD alternate.

  • An Executive Committee (EC) will be formed within the IRC to facilitate operation.

  • EPS will maintain the Roadmap web pages.

This Roadmap’s processes will be transparent and the work product will be published on the
EPS Web site and will be available to the Profession, Industry, Academia and
Research Institutes without charge.

top of page

Heterogeneous Integration Roadmap (HIR) Global Advisory Council

The HIR Global Advisory Council is established to provide the Heterogeneous Integration International Roadmap Committee (IRC) guidance in two important areas:

·         Advise HIR in defining and maintaining a long term vision of technology innovation required to support Industry progress over the next 15 years.

·         Advise HIR to ensure that its value proposition for stakeholders in industry, academia, research institutes and government is understood by and available to all.

Meetings will be scheduled semiannually, at minimum, as determined by the Council and the IRC. Additional meetings may be held as needed, to ensure the purpose is fulfilled.

The initial term of the council will be 3 years

Global Advisory Council members are nominated by the IRC and invited by the HIR Chair.

Current members of the Global Advisory Council include:

  • Ajit Manocha -  President and CEO of SEMI. Former CEO of GlobalFoundries and served as chair of SIA. Also served in executive roles at Philips/NXP & Spansion. 
  • Nicky Lu  - Founder and Chairman of Etron Technology in Taiwan. Served as chair of TSIA and WSC and is a member of the US National Academy of Engineering. 
  • Babak Sabi - Intel Corporation Corporate Vice President, General Manager, Assembly Test Technology Development.
  • Hubert Lakner -  Board of Directors Chairman, Fraunhofer Microelectronics Group and Founding Director of Fraunhofer Institute of Photonic Microsystems (IPMS) in Dresden. 


The IEEE EPS Heterogeneous Integration Roadmap will address the assembly & packaging, test and interconnect technologies required to meet industry needs over the next 15 years. The scope statement refers specifically to the 2019 edition of this Roadmap. It will be revised for each addition to define the changing scope of the Roadmap over time.

Packaging is the final manufacturing process transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for reliability. The rise of  the Internet of Things (IoT), movement to the cloud of data  logic and applications, the slowing of Moore’s Law scaling for CMOS and the realization that transistors at the geometries to be used will wear out all place new demands on the industry.

Design concepts, packaging architectures, device types, materials, manufacturing processes and systems integration technologies are all changing rapidly. These innovations have resulted in development of several new technologies as well as expansion and acceleration of technologies introduced in prior years. Heterogeneous integration with wireless and mixed signal devices, bio-chips, power devices, optoelectronics, and MEMS in a single package is placing new requirements on the industry as these diverse components are introduced as elements for System-in-Package (SiP) architectures.

The scope or the Heterogeneous Integration Roadmap is identification of the difficult challenges and the potential solutions for meeting technical requirements for the next 15 years and 25 years for emerging research areas. The primary integration technology for the potential solutions will be complex, 3D System in Package (SiP) architectures.

top of page


HI for Market Applications


High Performance Computing and Data Center


IoT  Modeling & Simulation

Medical, Health and Wearables 

Cross Cutting topics


Materials & Emerging Research Materials

Aerospace & Defense

Emerging Research Devices


Supply Chain

Heterogeneous Integration Components


Single Chip and Multi Chip Integration

Thermal Management

Integrated Photonics


Integrated Power Electronics Reliability

MEMS and Sensor Integration

Integration Processes

5G, RF and Analog Mixed Signal SiP and Module


Interconnects for 2D & 3D Architectures


WLP (fan in and fan out)

Please Read for more information on HIR TWGs

Please Read for more information on TWG Chapters

top of page


Heterogeneous Integration Panel at INTERPACK

The International Roadmap Committee has arranged for a series of face-to-face workshops around the world. This is done so that members of the TWGs will find it easy to attend at least one face-to-face meeting to support collaboration during Roadmap preparation by developing personal relationships. It is not intended that all TWG members attend each workshop although they will be invited. The list of workshops and the sponsoring organizations for each one is listed below.





A number of presentations on Roadmap activities were held in addition to the workshops. 

1.    ConFab Las Vegas, NV USA  06/14
2.    3D PEIM North Carolina, USA, 06/14
3.    IEMT-EMAP Penang, Malaysia  09/20- 22

Questions and Inquiries?

Become a contributing member of the Roadmap


top of page


 (updated: 8 February 2017)





Heterogeneous Integration Roadmap (HIR) Webinar Series (OPEN TO EVERYONE AT NO COST)

The electronics industry has reinvented itself through multiple disruptive changes in technologies, products, applications and markets. Our industry continues to evolve with the rapid migration of logic, memory, and applications to the cloud, the evolution of the Internet of Things (IoT) to the Internet of Everything (IoE), the proliferation of smart mobile devices everywhere, the rise of 5G, the increasing presence of microelectronics in wearables,  health applications, and  the rapidly evolving issues related to autonomous vehicles applications. Underlying all the changes are the rapid advancement of AI and the increasing abundance of data & data analytics.  The pace of innovation is  increasing to meet these challenges.

The Heterogeneous Integration Roadmap (HIR), released October 2019, is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. With the release of the 2019 HIR edition, the preparation of the 2020 edition is underway.

We are announcing the Heterogeneous Integration Webinar Series. The series is based upon the content of the 2019 HIR edition. The webinars will be delivered by the authors of the individual roadmap chapters. The primary purposes are to broaden the proliferation of the roadmap content to the profession and industry and to seek feedback from the roadmap users for inclusion into the 2020 edition2

Watch for the invitation or visit this website for schedule details and instructions about how to register. 

Please access the EPS Webinar Archive to acess past HIR webinars.

Download the 2019 Edition of the HIR

You may earn 1 Professional Development Hour for each webinar you attend, by completing the PDH survey form.

The list of events is currently unavailable.


Richard C. A. Pitwon received his first degree (BSc Hons) in Physics from the University of St Andrews in 2000 and MSc in Computer Science in 2001. He currently serves as Lead Photonics Engineer at Xyratex with over 13 years experience in the design and development of high speed photonic interconnect technologies including passive and active optical connectors, optical printed circuit boards, optical interconnect interfaces and transceivers. He holds 21 patents in the field of embedded optical interconnect and has authored numerous conference, journal and commercial publications in this area. He is a Chartered engineer (CEng) and expert member on the British Standards Institute (BSI) fibre-optics and electronic assembly subcommittees representing the UK on International Electrotechnical Commission (IEC) standards committees for optical interconnect technologies.