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Next Phase of Innovation: Heterogeneous Integration

 

Following SIA's closure of ITRS activities in 2015, the Heterogeneous Integration Roadmap activities will continue -- sponsored by the IEEE Electronics Packaging Society (EPS), SEMI, IEEE Electron Devices Society (EDS), IEEE Photonics Society and the ASME EPPD Division, with the intention of expanding the roadmap collaboration to other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.


Background
Mission
Purpose
Committee
Global Advisory Council
Scope
Schedule

BACKGROUND

The ITRS Assembly and Packaging Working Group has had many years of history of collaboration with the IEEE Societies in holding workshops and work sessions at IEEE Societies sponsored conferences and events around the world.  The basis of this collaboration is the common shared interest in a Technology Roadmap for the IEEE Societies’ membership, conference attendees and participants in the ITRS Technical Working Group work sessions.  IEEE Societies Conferences are high profile forums on the latest research and development in Packaging, Interconnect, Test and the materials, processes and equipment supporting this R&D. The Roadmap workshops of the ITRS had provided an opportunity for the participants to review the directions of these technologies and build a technology Roadmap looking 15 years into the future.

The collaboration in technical working groups (TWGs) that produced the ITRS Roadmap has continued with the establishment of the Heterogeneous Integration Focus Team in 2014. In 2015, a MOU was signed between the Heterogeneous Integration Focus Team and the IEEE EPS with the approval of the Semiconductor Industry Association (SIA) to ensure the collaboration was sustainable.

In the winter of 2015, SIA announced that it would bring the ITRS activities to a close with the publication of the 2015 Edition in the spring of 2016.

We believe that it is important to continue this Heterogeneous Integration Roadmap function for the profession, industry and the entire technical community. In the era of IoT, the Cloud, smart phones and intelligent automobiles, there is immense need for a pre-competitive technology roadmap providing a long term vision to the future and identifying difficult challenges and potential solutions. 

IEEE communities, including the IEEE Societies and Councils, are rich in creativity, innovation and knowledge across science, technology and arts associated with electronics. Bringing this mission under the auspices of the IEEE Technical Societies will fill this important need with the deep knowledge base from the Societies’ global membership and worldwide network. It would be a service to the global technical professionals and technical community consistent with the IEEE mission.  The goal for this roadmap is to be open and transparent. IEEE EPS provides institutional sponsorship to ensure sustainability and quality.

The Heterogeneous Integration Roadmap activities are sponsored by IEEE Electronics Packaging Society (EPS), SEMI,  IEEE Electron Devices Society (EDS),  IEEE Photonics Society and the ASME EPPD Division with the intention of expanding the roadmap collaboration to other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.  A document with definition of the mission, purpose, structure and governance for this Heterogeneous Integration Roadmap program was prepared and approved.


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MISSION STATEMENT

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly (SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub-system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level performance and cost of ownership.

The mission of this Heterogeneous Integration Roadmap is to provide guidance to the profession, industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics. That progress is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the requirements for heterogeneous integration in the electronics industry through 2031, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.


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PURPOSE OF INTERNATIONAL HETEROGENEOUS INTEGRATION ROADMAP

  • The Roadmap serves as a guideline for the global electronics industry of projected technology needs and opportunities for innovation.

  • The Roadmap is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment.

Serving the Profession, Industry, Academia and Research Institutes, the Roadmap provides:

  • A forecast of industry requirements to maintain the pace of progress for the industry and user community  over the next 15 years, and the next 25 years for the heterogeneous integration of emerging devices and materials which require a longer research development horizon.

  • Identification of difficult challenges that must be addressed to meet these industry requirements.

  • Where possible the Roadmap will identify research requirements and potential technical solutions.

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HETEROGENEOUS INTEGRATION ROADMAP COMMITTEE STRUCTURE AND GOVERNANCE

  • An International Roadmap Committee (IRC) has been established by the sponsoring organizations, under the oversight of the EPS Society.

  • The IRC will initially be a group of ~6 people with representation from EPS, EDS, Photonics, SEMI, ASME EPPD and other IEEE and non-IEEE collaborating organizations, government and academia.

  • The Chair of the IRC will be named by the EPS President.

  • The Co-Chair of the IRC will be chosen by vote from the IRC.

  • The IRC will meet at least quarterly and publish minutes of the meetings.

  • The IRC will determine the Technical Working Groups (TWGs) that will be established to develop chapters of the Roadmap, appoint the TWG Chairs and approve the mission and scope statements of each Roadmap chapter.

  • TWG chairs will be responsible for recruiting the appropriate volunteers to address the scope of their Roadmap chapters.

  • The Roadmap will participate in the same peer review and quality control procedures as other IEEE publications.

  • The schedule and location of meetings at Society Conferences will be determined by the IRC for:
    • In person meetings of the full Roadmap membership
    • On-line meetings for all TWG Chairs
  • TWG Chairs will schedule in person meetings and on-line meetings for their members working sessions and share their schedule with the IRC.

  • The IRC will determine the schedule for preparation and publication of the Roadmap.

  • The Current members of the International Roadmap Committee are: Bill Chen, Chair ; Bill Bottoms (IEEE EPS); Tom Salmon (SEMI), Subramanian Iyer (IEEE EDS), Amr Helmy (IEEE Photonics Society) and Ravi Mahajan (ASME EPPD Division). Gamal Refai-Ahmed is the ASME EPPD alternate.

  • An Executive Committee (EC) will be formed within the IRC to facilitate operation.

  • EPS will maintain the Roadmap web pages.

This Roadmap’s processes will be transparent and the work product will be published on the
EPS Web site and will be available to the Profession, Industry, Academia and
Research Institutes without charge.

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Heterogeneous Integration Roadmap (HIR) Global Advisory Council

The HIR Global Advisory Council is established to provide the Heterogeneous Integration International Roadmap Committee (IRC) guidance in two important areas:

·         Advise HIR in defining and maintaining a long term vision of technology innovation required to support Industry progress over the next 15 years.

·         Advise HIR to ensure that its value proposition for stakeholders in industry, academia, research institutes and government is understood by and available to all.

Meetings will be scheduled semiannually, at minimum, as determined by the Council and the IRC. Additional meetings may be held as needed, to ensure the purpose is fulfilled.

The initial term of the council will be 3 years

Global Advisory Council members are nominated by the IRC and invited by the HIR Chair.

Current members of the Global Advisory Council include:

  • Ajit Manocha -  President and CEO of SEMI. Former CEO of GlobalFoundries and served as chair of SIA. Also served in executive roles at Philips/NXP & Spansion. 
  • Nicky Lu  - Founder and Chairman of Etron Technology in Taiwan. Served as chair of TSIA and WSC and is a member of the US National Academy of Engineering. 
  • Babak Sabi - Intel Corporation Corporate Vice President, General Manager, Assembly Test Technology Development.
  • Hubert Lakner -  Board of Directors Chairman, Fraunhofer Microelectronics Group and Founding Director of Fraunhofer Institute of Photonic Microsystems (IPMS) in Dresden. 

SCOPE

The IEEE EPS Heterogeneous Integration Roadmap will address the assembly & packaging, test and interconnect technologies required to meet industry needs over the next 15 years. The scope statement refers specifically to the 2016 edition of this Roadmap. It will be revised for each addition to define the changing scope of the Roadmap over time.

Packaging is the final manufacturing process transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for reliability. The rise of  the Internet of Things (IoT), movement to the cloud of data  logic and applications, the slowing of Moore’s Law scaling for CMOS and the realization that transistors at the geometries to be used will wear out all place new demands on the industry.

Design concepts, packaging architectures, device types, materials, manufacturing processes and systems integration technologies are all changing rapidly. These innovations have resulted in development of several new technologies as well as expansion and acceleration of technologies introduced in prior years. Heterogeneous integration with wireless and mixed signal devices, bio-chips, power devices, optoelectronics, and MEMS in a single package is placing new requirements on the industry as these diverse components are introduced as elements for System-in-Package (SiP) architectures.

The scope or the Heterogeneous Integration Roadmap is identification of the difficult challenges and the potential solutions for meeting technical requirements for the next 15 years and 25 years for emerging research areas. The primary integration technology for the potential solutions will be complex, 3D System in Package (SiP) architectures.


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INITIAL TECHNICAL WORKING GROUPS (TWGs)

The IRC is preparing an initial list of TWGs being considered.

  • HI for Market Applications
    • High Performance Computing and Data Center
    • IoT 
    • Medical, Health and Wearables 
    • Automotive
    • Aerospace and Defense
    • Mobile
  • Heterogeneous Integration Components
    • Single Chip and Multi Chip Packaging (including Substrates)
    • Integrated Photonics
    • Integrated Power Electronics
    • MEMS & Sensor Integration
    • RF and Analog Mixed Signal
  • Design
    • Co-Design and Simulation 
  • Cross Cutting topics
    • Materials & Emerging Research Materials
    • Emerging Research Devices
    • Interconnect
    • Test
    • Supply Chain
    • Security
    • Thermal Management
  • Integration Processes
    • SiP & Module
    • 3D +2.5D
    • WLP (fan in and fan out)

Please Read for more information on HIR TWGs

Please Read for more information on TWG Chapters

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2018 SCHEDULE OF HIR WORKSHOPS

The International Roadmap Committee has arranged for a series of face-to-face workshops around the world. This is done so that members of the TWGs will find it easy to attend at least one face-to-face meeting to support collaboration during Roadmap preparation by developing personal relationships. It is not intended that all TWG members attend each workshop although they will be invited. The list of workshops and the sponsoring organizations for each one is listed below.

 
1.   European-3D Summit Dresden, Germany 1/22-24/2018
2.   Heterogeneous Integration Roadmap Symposium Santa Clara, CA 2/22/2018
3.   EuroSime Toulouse, France 4/15-18/2018
4.   ConFab, Las Vegas, NV 5/20-23/2018
5.   ECTC San Diego, CA 5/29-6/1/2018
6.   NordPac Oulu, Finland 6/12-14/2018
7.   SEMICON West San Francisco, CA 7/9/2018 Agenda
8.   ICEPT Shanghai, China 8/8-11/2018
9. HIR Workshop with EPS Japan, JIEP & SEMI Japan  Tokyo, Japan TBD
10. ITRI Hsinchu, Taiwan TBD
10. INTERPACK 2018 San Fancisco, CA 8/27-30/2018
12. IEMT  Melaka, Malaysia 9/4-9/2018
13. Electronics Packaging Symposium Binghamton, NY 9/18-19/2018 
14. ESTC Dresden, Germany 9/18-21/2018
15. IEEE Photonics Conference Reston, Virginia 9/30-10/4/2018
16. IMPACT Taipei, Taiwan 10/24-26/2018
17. Heterogeneous Integration Workshop 11/5/2018
18, SEMICON Europa  Munich, Germany 11/13-16/2018 
19. ICSJ  Kyoto, Japan 11/19-21/2018
20. IEDM  San Francisco, CA 12/2/2018 
21. EPTC Singapore 12/4-7/2018
22. SEMICON Japan  Big Sight Tokyo, Japan 12/12-14/2018

 

2017 SCHEDULE OF HIR WORKSHOPS

1.   EuroSIME Dresden, Germany 4/6
2.   ICEP 2017 (JIEP) Yamagata Japan 4/19-22
3.   ECTC  Orlando, FL,  USA  5/30-6/04
4.   JIC  (Jisso International Council) Spring Meeting 6/12
5.   NordPac Gothenburg, Sweden 6/18-20
6.   Palo Alto Workshop before SEMICON WEST, Palo Alto, CA, USA  7/9
7.   SEMICON WEST San Francisco, CA USA  7/10
8.   InterPACK (ASME)  San Francisco, CA, USA  8/29-9/1
9.   ELECTRONICS PACKAGING SYMPOSIUM , Niskayuna NY, USA 9/19-20
10. IEEE PHOTONICS CONFERENCE Lake Buena Vista, FL, USA, 10/1-5
11.  HIR Workshop in association with AIM Photonics Fall 2017 Meeting, Albany, NY 10/10-12
12.  IMPACT Taipei, Taiwan  10/25-26
13. First Annual Heterogeneous Integration Workshop at UCLA 11/1
14. ICSJ Kyoto, Japan 11/20-22
15. EPTC Singapore 12/3-5
16. IEDM San Francisco, CA USA 12/3
17. SEMICON Japan at Tokyo Big Sight  12/13
18. Asia Workshops
       A. ICEPT, Harbin China  8/17
       B. Tokyo workshop with CPMT Japan, JIEPS & SEMI Japan 8/10
       C. ITRI Hsinchu, Taiwan 8/11
       D. Hong Kong Workshop 8/14

2016 SCHEDULE OF HIR WORKSHOPS

  1. ECTC + ITHERM Las Vegas, NV USA 05/31- 06/04
  2. Palo Alto Workshop before SEMICON WEST (3101 Alexis Drive, Palo Alto. CA ) 07/10
  3. SEMICON WEST San Francisco, CA USA 07/11
  4. Nagase R&D Center Tokyo, Japan 8/9
  5. ITRI Taiwan 8/12
  6. ICEPT Wuhan, China 8/16
  7. ESTC Grenoble, France   09/13-16
  8. IEMT-EMAP Penang, Malaysia 9/20
  9.  Electronics Packaging Symposium Binghamton, NY USA 10/5-8
  10.  IMPACT Taipei, Taiwan  10/26-28
  11.  ICSJ Kyoto, Japan 11/7-9
  12.  MEPTEC Heterogeneous Integration Roadmap Symposium San Jose CA 11/14
  13.  EPTC Singapore 11/30-12/03
  14.  IEDM San Francisco CA 12/3-7
  15. Asia Workshops
    1. ITRI, Taiwan 8/12
    2. ICEPT in Wuhan, China 8/16-19
    3. Japan, Tokyo 8/9

A number of presentations on Roadmap activities were held in addition to the workshops. 

1.    ConFab Las Vegas, NV USA  06/14
2.    3D PEIM North Carolina, USA, 06/14
3.    IEMT-EMAP Penang, Malaysia  09/20- 22

Questions and Inquiries?

Become a contributing member of the Roadmap

 



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 (updated: 8 February 2017)

 

 

Attend lectures on the latest technology development topics within the EPS’s scope, presented by experts in our field -- through EPS Webinars.  No travel required.

Available to EPS Members only -- as a Member benefit, with no cost to you.

Recordings of and/or presentations from past Webinars can be accessed by EPS Members in the EPS Webinar Archive.

Professional Development Hours are now available for EPS webinars

Upcoming Webinars

Title: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration

Presenter: Dr. Ning-Cheng Lee

Date: November 20, 2018

Time: 11:00 AM EST

Register Here

Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form

Abstract: This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in details, and novel alloys with high reliability will be presented.  The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability.

 Bio: Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. In addition, he also has very extensive experience in the development of underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973.

Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies” by Newnes, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials” by McGraw-Hill. He is also the author of book chapters for several lead-free soldering books. He received 1991 award from SMT Magazine and 1993 and 2001 awards for best proceedings papers of SMI or SMTA International Conferences, 2008 and 2014 awards from IPC for Honorable Mention Paper – USA Award of APEX conference, and 2010 Best Paper Award of SMTA China South Conference.  He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow. He has served on the board of governors for CPMT and SMTA board of directors. Among other editorial responsibilities, he serves as editorial advisory board of Soldering and Surface Mount Technology, Global SMT & Packaging and as associate editor for IEEE Transactions on Components Packaging Manufacturing Technology.  He has numerous publications and frequently gives presentations, invited to seminars, keynote speeches and short courses worldwide on those subjects at international conferences and symposiums. 

 

Title: TSV and FOWLP Reliability Challenge Overview

Presenter: Darvin Edwards

Date: November 29, 2018

Time: 11:00 AM EST

Register Here 

Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form

Abstract:  Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two of the most rapidly growing package technologies in today’s semiconductor industry.  These package technologies borrow from past packaging processes with many novel additional improvements and refinements to meet the new application needs.  New or refined wafer fab and package processes include deep TSV drilling, TSV plating, wafer thinning, backside interconnect fabrication, thermo-compression Cu pillar bonding, capillary and molded underfilling, over molding, temporary carrier attach, and thin die pick-and-place among many others.  As with any new package technology, reliability risks must be evaluated with special emphasis on failure mechanisms that might arise from the new package configurations and applications.  The package design and process development engineer must understand the factors that play into new technology reliability failure mechanisms, as well as mitigations that can be employed to ensure that highly reliable products can be produced.  Without this knowledge, reliability failures are bound to occur.

This webinar will briefly review current predominant fabrication processes for both TSVs and FOWLPs.  Major TSV reliability risks such as Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, underfill voids, wafer backside contamination, and thermal issues will be addressed with multiple solutions provided.  The FOWLP discussion will highlight chip first vs. chip last issues such as chip shifting and warpage and will draw comparisons between FOWLP board level thermal cycling and drop reliability vs. FCBGAs and WLCSPs.  Example finite element modeling and experimental studies will be presented to illustrate the steps that must be taken to insure reliability has been designed in as the package processes are being developed. 

Bio: Mr. Darvin Edwards has 38 years of experience in the IC packaging industry.  He is currently owner of Edwards’ Enterprise Consulting LLC which specializes in helping companies solve package reliability problems, assisting in rapid product development, as well as providing worldwide training on topics such as package reliability, materials, TSV and FOWLP technologies, package design and surface mount techniques.  Previously, he worked 14 years as a Fellow at Texas Instruments, managing the Dallas electrical, thermal and thermomechanical modeling team responsible for chip-package interactions and reliability of multiple TI product lines.  He has served the IEEE EPS as Member at Large and is the co-chair of the Electronics Components and Technology Conference Applied Reliability committee.  Mr. Edwards has authored and co-authored over 65 papers and articles in the field of IC packaging, has written two book chapters, and holds 24 US patents.  He is an IEEE Senior Member.