Maximizing Benefits of Adaptive Test Techniques by Integration of ML and Test Infrastructure Improvements

Abhijit Sathaye

Principal Engineer

Manufacturing and Product Engineering

Intel Corporation

Hillsboro, OR, USA

abhijit.sathaye@intel.com

Abstract:

Testing Si devices in high volume manufacturing (HVM) is getting more challenging and expensive, owing to the increasing complexity of the devices under test. Semiconductor companies are adding more capabilities on a package, transistor density is going up, end user applications are more varied than ever before.