Santa Clara Valley Chapter Upcoming Events
Electronics Packaging Chapter
Tutorial: Reliability Testing and Design for Reliability of Packaging Interconnects
-- 2-Hour Short Course: lead-free solder joints, power creep, viscoplasticity, temperature, strain rate, constitutive equations, thermal-cycling, examples, recommendations ...
Speaker: John H Lau, Unimicron Technology Corporation
Date: Thursday, January 5, 2023
Time: Checkin via WebEx at 7:45 AM (PST); Presentation 8:00 – 10:00 AM (PST)
Cost: none
vTools Information: https://events.vtools.ieee.org/m/336536
Registration: https://r6.ieee.org/scv-eps/?p=2996
Summary: Recent advances and trends in lead-free solder joint reliability are presented in this study. Emphasis is placed on the design for reliability (DFR) and reliability testing and data analysis, including: Norton power creep constitutive equations and examples; the Wises two power creep constitutive equations and examples; the Garofalo hyperbolic sine creep constitutive equations and examples; and the Anand viscoplasticity constitutive equations and examples, with temperature and strain rate-dependent parameters. For reliability testing and data analysis, the Weibull and lognormal life distributions for lead-free solder joints under thermal-cycling and drop tests; the true Weibull slope, true characteristic life, and true mean life; and the linear acceleration factors for various lead-free solder alloys based on frequency and maximum temperature, dwell time and maximum temperature; and frequency and mean temperature will be presented. Some recommendations will also be provided.
Electronics Packaging Chapter
Thermal and Failure Analysis of Advanced Sub-Micron Devices
-- thermal imaging, fine-geometry, static/dynamic, high-resolution, thermoreflectance, near-ultraviolet to infrared, examples ...
Speaker: Dr. Mo Shakouri, Microsanj Corp.
Date: Thursday, January 26, 2023
Location: in person at SEMI World Hdqtrs, Milpitas, CA USA (and via WebEx)
Time: Checkin at SEMI (sandwiches and drinks) at 11:30 AM (PST); Presentation at noon (PST). WebEx at noon.
Cost: none
vTools Information: https://events.vtools.ieee.org/m/336546
Registration: https://r6.ieee.org/scv-eps/?p=2998
Summary: Performance requirements for today’s semiconductor and optoelectronic devices are leading to shrinking geometries, more complex 3-dimensional structures, and new materials. High temperatures, hot spots and temperature spikes can have a major impact on reliability. It is essential that one have a thorough understanding of static and dynamic thermal performance under operating and static conditions. This has traditionally been complex, time consuming, and often lacked the resolution required to detect thermal anomalies that could lead to early device failures. Fortunately, advances in thermal imaging techniques that combine the benefits of thermoreflectance-based analysis with illumination wavelengths from near-ultraviolet to near infrared coupled with infrared thermography can support thermal, spatial, and transient resolution consistent with today’s advanced complex device structures and shrinking geometries. In addition, equipment has advanced to considerably reduce the time and cost to get accurate results. Many examples will be shared to fully illustrate the device thermal behaviors that can be detected with these advanced thermal analysis techniques.