EDS Sponsored Webinar Offered to EPS Members

Title: Heterogeneous Integration - why is it becoming such a big deal and how does it affect electron device development

Date: 22 July 2020 

Time: 11:00 AM EDT - Register Here

Presenter: Subramanian S. Iyer


If you take any printed circuit board (PCB) today, it is already more than likely an example of heterogeneous Integration.So in truth, Heterogeneous Integration is not really new. So why this new found hype ? In this talk, we describe what needs to be different about heterogeneous integration by trying to address some key differences between the new heterogeneous integration and the ones of bygone eras: What is the optimal size of chiplets or more correctly dielets; what is the optimal pitch at which they need to be connected; How close must we connect them; and how large should we make such integrated units and finally what are the possible showstoppers as we boldly march into this new era. An important implication for those working in the device and integration area: don't kill yourself trying to put everything on one mega chip. It's getting more and more difficult and expensive. We can get equivalent or better results in most cases using heterogeneous dielet integration at fine pitch and close spacing. As they say " small is beautiful and vive la difference!"


Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and architectures that they may enable including in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.