Fan-out wafer-level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wire bond and bump interconnections, substrates, leadframes, and the traditional flip-chip or wire bond chip attach and underfill assembly technologies across multiple applications. The next step is economy of scale: the conversion from 300mm to panel Panel Fan-Out. This topic was discussed at IEEE Electronics Package Society’s Electronic System-Integration Technology Conference (ESTC) conference in Dresden, Germany, on September 19, 2018. In a panel called “ESTC called “Fan-Out Panel: Is the Industry Ready?” panelists Jan Vardaman of TechSearch International, Tanja Braun, Ph.D., of Fraunhofer IZM, Marion Weigand of HDMicrosystems, and Jan Kellar of Deca Technologies and chaired by Beth Keser, Ph.D., of Intel Corporation, discussed how their company or consortium is addressing (or not addressing) the panel fan-out market and discussedthe intersection with European markets such as automotive, IoT, and flexible electronics. Not coincidentally, this was an all-female technical panel, the first of its kind in the electronic packaging industry.
L to R: Marion Weigand, Tanja Braun Ph.D., Jan Vardaman, Jan Kellar, and Beth Keser, Ph.D. at ESTC 2018, Dresden, Germany.