Santa Clara Valley Chapter Upcoming Events
Electronics Packaging Chapter
Thermal and Failure Analysis of Advanced Sub-Micron Devices
-- thermal imaging, fine-geometry, static/dynamic, high-resolution, thermoreflectance, near-ultraviolet to infrared, examples ...
Speaker: Dr. Mo Shakouri, Microsanj Corp.
Date: Thursday, January 26, 2023
Location: in person at SEMI World Hdqtrs, Milpitas, CA USA (and via WebEx)
Time: Checkin at SEMI (sandwiches and drinks) at 11:30 AM; Presentation at noon (PST). WebEx at noon.
Cost: none
vTools Information: https://events.vtools.ieee.org/m/336546
Registration: https://r6.ieee.org/scv-eps/?p=2998
Summary: Performance requirements for today’s semiconductor and optoelectronic devices are leading to shrinking geometries, more complex 3-dimensional structures, and new materials. High temperatures, hot spots and temperature spikes can have a major impact on reliability. It is essential that one have a thorough understanding of static and dynamic thermal performance under operating and static conditions. This has traditionally been complex, time consuming, and often lacked the resolution required to detect thermal anomalies that could lead to early device failures. Fortunately, advances in thermal imaging techniques that combine the benefits of thermoreflectance-based analysis with illumination wavelengths from near-ultraviolet to near infrared coupled with infrared thermography can support thermal, spatial, and transient resolution consistent with today’s advanced complex device structures and shrinking geometries. In addition, equipment has advanced to considerably reduce the time and cost to get accurate results. Many examples will be shared to fully illustrate the device thermal behaviors that can be detected with these advanced thermal analysis techniques.
Electronics Packaging Chapter, with ASME and SEMI
Sixth Annual Symposium on Heterogeneous Integration
-- Purpose and Future Vision for Heterogeneous Integration from Global Perspectives, 3 days, 8 plenary talks, working groups ...
Dates: Wednesday, February 22 (tutorials); Thursday-Friday, February 23-24, 2023 (Symposium)
Location: in person only, at SEMI World Hdqtrs, Milpitas, CA USA
Cost: TBD (approx. US$60)
vTools Information: https://events.vtools.ieee.org/m/336609
Registration: https://r6.ieee.org/scv-eps/?p=3003
Summary: Two pre-symposium tutorials on chiplets, tutorial on three NIST-sponsored Roadmaps; Invited Plenary Presentations "Critical Issues in Electronics Resurgence for next decade & beyond"; Key messages from groupings of the HIR Chapters (with cross-TWG panels); Cross TWG Collaboration & Dialogue; Planning for 2023 conference events, workshops & collaboration.