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 Term 1 January 2025 through 31 December 2027


Nomination Form

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Regions 1-7 & 9 vote for Members-at-Large from Regions 1-7 & 9, members in Region 8 vote for Members-at-Large from Region 8, and members in Region 10 vote for Members-at-Large from Region 10).

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Title: Addressing Electromagnetic Simulation Challenges for Multi-Die 2.5D/3DIC Designs

Date: 24 May, 2024 (Friday)

Time: 8:00 AM PDT

Speaker: Dr. Feng Ling (feng.ling@xpeedic.com)

Moderator: Kemal Aygun

Register Here

Short abstract:

The emergence of multi-die 2.5D/3D IC designs requires fundamental changes for conventional EDA tools and methodologies in terms of system-level architectural exploration, physical implementation, analysis and sign-off, verification, and design for manufacturing. This talk will focus on the challenges and solution for signal integrity analysis of 2.5D/3D multi-die packages. A novel electromagnetic solver delivering unprecedented performance advantages with uncompromised accuracy will be introduced. Benchmark examples on various advanced packaging platforms demonstrate its accuracy and efficiency.

Presenter's Bio:

Dr. Feng Ling. Feng Ling is the founder and CEO of Xpeedic, a leading simulation EDA provider for IC, package, and system designs. Dr. Ling has over 20 years’ industry experience spanning from Motorola SPS (now NXP) to EDA startups Neolinear (acquired by Cadence), Physware (acquired by Siemens EDA) and Xpeedic. Dr. Ling received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2000. He is a Senior Member of IEEE. He has authored and co-authored 3 book chapters and more than 60 papers in refereed journals and conference proceedings.

PSMA International Energy Harvesting Workshop ~ 26-28 June, 2024, Perugia, Italy

EnerHarv 2024 will bring together experts from around the world, in its third installment of working on all technical areas relevant to energy harvesting, power management and its IoT applications (https://www.EnerHarv.com). This non-profit workshop, organized and sponsored by the Power Sources Manufacturers Association (PSMA, https://www.psma.com/), will be held at Hotel Giò Congress Center in majestic city of Perugia, Italy from June 26 to 28. The event shall be hosted by the Noise in Physical Systems (NiPS Lab) of University of Perugia (UNIPG, https://www.unipg.it/en/).

It will comprise presentations (invite only), demos, poster, panels sessions and generous amounts of time for networking activities.

NEW IN 2024: dedicated booklet (with professional reference, DOI, ISBN, etc.) of proceedings for optional opportunity to include supporting materials optional to those presented live at the workshop. There is an OPEN call for demonstrations and posters (until May 31).

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IEEE ESTC 2024 – The place to be!

Be a part of IEEE ESTC 2024 – the premier international event in the field of microelectronics and system integration, including their application in industry. The conference t is organized every two years in Europe and is sponsored by IEEE-EPS in association with IMAPS Europe. This year it takes place in Berlin, Germany, from September 11-13, 2024. As we are finalizing the program, we would like to give you an overview of the program highlights.

Conference program now online!

This year’s IEEE ESTC Conference will feature roughly 120 oral and 70 poster presentations highlighting new developments in advanced packaging, wafer-level packaging, reliability of electronic devices and power electronics, to name but a few topics. As in previous years, the conference papers will be published in the conference proceedings and in the IEEE Xplore database.

The conference program is available on our website at https://www.estc-conference.net/.

Other highlights in the conference program include four professional development courses on the morning of the first conference day, an EPS HIR Workshop, Special Sessions on ChipsAct and IPCEI project, Photonics and Quantum Computing, Education and Green ICT as well as a Panel Discussion on “Chiplet Architectures for Automotive“.

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13th IEEE CPMT Symposium Japan (ICSJ2024)

“Innovation of Packaging Technology for Advanced Heterogeneous Integration”

November 13 -15, 2024

Ritsumeikan University Suzaku Campus, Kyoto, JAPAN


IEEE CPMT Symposium Japan (ICSJ) is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. ICSJ provides a platform for you to communicate and interact with global leaders in packaging technology. ICSJ2024 is only on-site conference.

Innovation of Packaging Technology for Advanced Heterogeneous Integration: Semiconductor devices have contributed to the development of various fields including PCs, because the pursuit of miniaturization (More Moore) has made it possible to simultaneously meet the demands for high speed, lower power consumption, and lower cost. On the other hand, the limit for miniaturization of silicon CMOS transistors is approaching and we are now pursuing a new axis of development called “More than Moore”, which is evolving in the direction of functional diversification. Indeed, heterogeneous integration is attracting attention as the key to the continued growth of the semiconductor industry. Integrating heterogeneous materials, devices, and circuits (e.g., analog/RF,passives,Si photonics,sensors/MEMS, biochips) into a 3D system-in-package is becoming widespread as the productivity driver. Furthermore, In the post-Moore’s Law era of the semiconductor industry, heterogeneous integration and chiplet-based approaches through the advanced 2.5D and 3D packaging technology such as a die-to-die (D2D), die-to-wafer (D2W) wafer-to wafer (W2W) hybrid bonding will play a crucial role for high-end applications including high-performance computing (HPC), artificial intelligence (AI), servers, and data centers. In 2024, our focus is on key electronics packaging technologies for advanced heterogeneous integration and emphasizes on the following main topics: Photonics, Advanced Packaging, Process & Material, Power & Automotive Electronics, Bioelectronics & Healthcare, and Signal/Power Integrity. 

Authors are invited to submit an abstract through our website https://www.ieee-csj.org.

The abstract submission deadline is May 31, 2024. 

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The 13th IEEE International 3D Systems Integration Conference 2024 (3DIC2024)

25 September 25 (Wed.) to 27 September (Fri.),

Hotel Metropolitan Sendai and Sendai Kokusai Hotel, Japan


The 13th IEEE International 3D Systems Integration Conference 2024 (3DIC2024) will be held from September 25 (Wed.) to 27 (Fri.), 2024, at Hotel Metropolitan Sendai and Sendai Kokusai Hotel.

This conference is a continuation of the first international conference on 3DIC held in Japan, 3D-SIC2007, in March 2007 under the auspices of the Advanced Science and Engineering Technology Development Organization (ASET). Since 2009, the conference has been held annually in Japan, Europe, and the United States in rotation, sponsored by the IEEE. The research on 3D-IC/Chiplet and system integration requires a wide range of knowledge. Therefore, we will continue to develop and implement 3D-IC/Chiplet and system integration. This conference enables active discussions that transcend specialized areas, encourages dedicated participation by professionals and young researchers, and aims to develop this. The Best Young Researcher or Student Award will be presented on the final day. We believe that many of you will contribute to the conference.

Please submit one page of text (500 words) and one page of figures as an abstract.

The deadline for abstract submission is Friday, June 14, 2024.

Click here for Call for Papers details.

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33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems


Dear Colleague,

A month is left to submit your work to EPEPS 2024 this October, and apply for student grants! We invite you to:

submit a paper and compete for four conference awards! Deadline: June 14, 2024

apply to 15+ grants for graduate students and young professionals, sponsored by the EPS and MTT societies. If selected, you’ll receive free registration and a travel allowance to join EPEPS 2024. Deadline: June 14, 2024

apply to sponsorship & exhibitor opportunities, and promote your company in one of the world’s largest tech hubs. 

There are many reasons to join EPEPS 2024:

 • top-notch 4-day program, with 3 keynotes, presentations, posters and demo sessions focused on the latest advancements from academia and industry;

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“Advances in Heterogeneous Integration for Neuromorphic Computing”

Artificial intelligence (AI) is currently in its third wave of development, while the traditional von Neumann architecture faces challenges in highly parallel computing, energy efficiency, and ultra-low power consumption. Neuromorphic computing provides a solution by mimicking the structure and functions of the human brain to potentially overcome the limitations of traditional computer architecture and enhance the computing capabilities for AI tasks. The human brain demonstrates remarkable efficiency, with over 100 billion neurons and approximately 100 trillion synapses, all while consuming only about 20 Watts of power. Replicating this biological marvel in hardware involves numerous different components (sensors, memory, computing, communication macros) and various technologies (PCM, RRAM, different technology nodes, analog/digital designs). Heterogeneous integration provides the opportunity to integrate various functionalities into neuromorphic computing systems.

This Special Section will focus on neuromorphic computing systems by providing space for cutting edge research addressing challenges, opportunities, and trends in their modeling, measurement, and design. We encourage all techniques and applications within the realm of neuromorphic computing systems, encompassing materials, devices, circuits, packaging, and their electrical, thermal, and reliability performance. Suggested areas include the development and evolution of

A. Novel intelligent materials and devices, along with integration techniques at the device level for neuromorphic computing.

B. Advanced analog, digital, and mixed-signal circuits, and architectures to achieve high-performance neuromorphic computing applications.

C. Novel system integration techniques for neuromorphic computing, focusing on advanced 2.5D and 3D packaging technologies.

D. Techniques addressing electrical, thermal, and reliability challenges, such as I/O routing, heat dissipation, and signal and power delivery as they pertain to neuromorphic systems.

E. Co-design approaches across multiple disciplines, spanning materials, devices, circuits, architectures, and integration, for neuromorphic chips.

Paper submission deadline: August 31, 2024.

Final manuscripts due: January 31, 2025.

Planned publication date: March 2025.

On-line submission procedure for the authors: Authors should use the IEEE T-CPMT Author Portal to submit the manuscripts and select "Special Section on Neuromorphic Computing" when submitting the papers. Please note the same in the cover letter to ensure that the manuscript is assigned correctly. All papers are to conform to IEEE TCPMT Guidelines.

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Abstract: As devices for quantum computing, AI hardware, power electronics, and magnetics mature enough to be commercialized, their unique packaging challenges must also be considered and solved. Advanced microelectronics technology platforms call for advanced packaging solutions, and these packages are not focused on traditional pitch scaling for high I/O count. Here, we discuss the distinctive packaging concerns around these emerging microelectronic devices, as well as avenues to address them. 


Keywords microelectronics, quantum Keywords microelectronics, quantum, superconductors, integrated photonics, magnetic memory, artificial intelligence hardware, power electronics, trapped ions



 While much of the semiconductor industry and attention to the microelectronics industry is focused on silicon-based transistors for logic and memory applications, other materials, device types, and chip architectures are leveraging the ecosystem. Recently, the United States Government decided to invest heavily in the semiconductor space through the CHIPS and Science Act, which primarily encourages domestic microelectronics manufacturing and advanced R&D. For their working to accelerate the transition of microelectronics technology that are relevant to the DoD from the prototype stage to manufacturing relevance. The program looks to accelerate the -tocapabilities within these hubs.

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David Geb

Subodh Deodhar

Nitin Netake

Tejas Jeurkar





Ansys, Inc.


Dynamic thermal management (DTM) generally allows dynamic manipulation of hardware or software to better handle extreme usage scenarios, thereby enabling improved design with lower size, weight, power, and cost (SWaP-C).  DTM has received increased interest among the thermal management community, and a DTM Workshop was hosted at DARPA in September, 2023 [1].  DTM can involve passive approaches such as using phase-change materials (PCM), fluids operating near and in the 2-phase regime, and heat pipes.  Alternatively, DTM can involve active approaches employing thermostat control, such as fans or blowers, thermoelectric coolers (TECs), and power throttling with, for example, dynamic voltage and frequency scaling (DVFS).  The latter approach, power throttling with DVFS and simulation to support optimal placement of on-chip thermal sensors, has been noted as a key thermal simulation challenge for advanced 3D ICs in the Heterogeneous Integration Roadmap (HIR) [2], and will hence be the focus of this paper.


The switching power dissipated by a chip is strongly dependent on voltage and frequency and can be reduced by scaling down these quantities. This leads to DVFS being an effective power management technique that throttles processor power based on live, dynamic conditions [3-4].  Typically, DVFS can be used to conserve power consumption (e.g., for longer battery life in mobile devices), reduce the heat generation on the chip when temperatures are too high, resulting in a decreased cost of the thermal management solution (such as a smaller heat sink) and improved reliability, or reduce noise by allowing fans to run at lower speeds such as in server applications.  Power throttling with DVFS has been applied to applications ranging from low-power mobile processors [5] to high-power server chips [6-7], and from single chips to 3D IC systems [8-9].

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