3D Die-to-Die Interconnect Testing Challenges and the Need for an IEEE Standard

Sreejit Chakravarty, IEEE Fellow

Principal Engineer, Intel Corporation


Introduction. The increasing trend to integrate and package multiple dice into one SoC has been driven by yield, i.e. cost, considerations, need to integrate proprietary functionality from different sources into the SoC, etc. Semiconductor manufacturers responded by developing innovative interconnect and packaging technologies, including 2.5D and 3D variants. In 2.5D, dice are placed next to each other on a substrate and interconnected using special IOs.

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