Title: Overview of the Co-Design Chapter of the Heterogeneous Integration Roadmap
Date: July 23, 2020
Time: 11:00 AM EDT - Register Here
Presenters: Professor José Schutt-Ainé and Professor Rohit Sharma
This talk focuses on current state-of-the-art, challenges and potential solutions for Co-Design. Electrical, thermal, and mechanical interactions across the chip-package-board domains can no longer be ignored. New modelling and simulation tools must accurately predict the physical (e.g. electro-thermal, thermo-mechanical, etc) coupling between multiple semiconductor components and the package/system that contains them. The Co-Design Chapter of the Heterogenous Integration Roadmap explores how design and analysis practices need to be defined in the context of heterogeneous integration. It addresses the traditional chip-package-board design flow as well as current capabilities and future challenges. The vision is to create an environment where design closure is achieved with a minimum number of iterations meeting all requirements for performance and cost. This environment must leverage from currently available technologies, namely computing power, algorithms and artificial intelligence.