M Farooq
Mukta Farooq (M’10-SM’12-F’16) Dr. Mukta Farooq is an IBM Distinguished Research Scientist, IBM Lifetime Master Inventor with 232 granted US Patents, and a member of the IBM Academy of Technology. She is an IEEE Fellow, and a Distinguished Alumna of IIT Bombay. She is currently the Heterogeneous Integration Technology Leader at IBM Research, working on 2 nm CMOS 3D TSV integration and fine pitch die-stacking for AI Computing.
Her expertise includes semiconductor materials and structures, Heterogeneous Integration, 3-Dimensional (3D) Integration, flip-chip and die stacking technology, lead-free alloys, C4, Cu hybrid bonding, micropillar, ball / column grid arrays, chip package interaction, CMOS FET BEOL (Back End of Line) processing, packaging technology, and intellectual property development. She was awarded an Outstanding Technical Achievement Award for her pioneering and sustained contributions to IBM's 3D Technology.
She has several patents designated as high value because of their use in semiconductor manufacturing. Her patents and intellectual property contributions are in multiple areas of semiconductors and microelectronics packaging: (1) Lead-free alloys and structures for C4, Ball Grid and Column Grid Arrays (2) Crackstop and chip package interaction improvement structures and processes (3) High BEOL TSV integration and evaluation (4) TSV proximity effect mitigation structures (5) Wafer level bonding structures to enable tight die-die coupling (6) Bond and assembly (7) Capillary underfills (8) Heterogeneous Integration structures including surface bridges, die-stacking, wafer level processing (9) Architectures enabling AI compute. Key portions of this IP and know-how have been used in IBM mainframes and in several products such as the Hybrid Memory Cube [© Micron Technology] logic controller. Some of this IP is planned to be deployed in future generations of IBM AI Units.
Mukta has contributed technology papers to major conferences [such as ECTC 2022, IRPS 2015, IEDM 2011], given invited talks/papers [iMAPS, IRPS, others], and taught short courses at key technical conferences [3D Integration courses at IEDM, EDTM, SEMICON West, and the SOI-3D-Sub Vt conference].
Mukta is the Founding Member and current Chair of the EPS Mid-Hudson Valley Chapter that has membership along the Hudson Valley area, from Albany to Yorktown Heights, New York. She has organized with other volunteers several lectures and mini symposia in advanced packaging technology. She is also on the EPS Fellows Evaluation Committee [2023 and 2024]. She is an IEEE EDS Distinguished Lecturer and an invited lecturer to Women in EDS. Mukta has previously served 2 terms [3 years each] as an elected Member at Large of the Electron Device Society Board of Governor, and has actively supported EDS for the last 15 years, including as Chair of the EDS Mid Hudson Chapter. Mukta was awarded the 2022 IEEE EPS award for sustained lifetime contributions to electronic packaging. In 2021, she received the IEEE Region 1 Technological Innovation Award. She is active in mentoring professionals in engineering & technology.
Mukta holds a Ph.D. in Materials Science & Engineering from Rensselaer Polytechnic Institute, an M.S. in Materials Science from Northwestern University, and a B.Tech [Technology] in Metallurgical Engineering from the Indian Institute of Technology, Bombay.