Upcoming Webinar: Test Technology for Heterogeneous Integration
Date: July 2, 2020
Time: 11:00 AM EDT - Register Here
Presenter: Dave Armstrong, Don Blair, Ken Lanier and Marc Hunter
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Abstract:
The Test Technology chapter of the HIR highlights the challenges and opportunities for the semiconductor industry as we move forward. The chapter itself is divided into 15 different white papers because of the significant diversity of different challenges the test industry must face. Whether it’s a single cell phone SIP with incredible complexity or a use-once medical sensor where incredible accuracy is life-critical the test industry must meet the needs.
With the significant recent increases in internet traffic, efficient testing of big-digital AI, server, and communications devices is more critical than ever before. Marc Hutner will discuss how logic test is confronting this challenge, including a discussion on how design-for-test (DFT) is both challenging and helping the industry as we move forward.
The roll out of 5G mobile phone devices is anticipated to be a world-changing advancement. Meeting this need requires many advancements in the test technology of RF devices. Don Blair will provide an overview of how the test industry is changing in order to meet these challenges.
It is really difficult for the industry to maintain a cost-effective test cost when device complexity is growing in so rapidly and in so many directions. The number of transistors per piece of silicon continues to grow. The number of die per package now accelerates this transistor growth exponentially. Additionally, test must evolve in very many different domains, some quite new and difficult; (Logic, RF, Photonic, Memory, Thermal, Sensors, Analog, Reliability, 3D, System Level, Automotive, Quantum, Medical, etc.) All this does make it difficult to keep the cost-of-test from skyrocketing. Ken Lanier will discuss steps the industry is taking to meet these challenges and what the results and forecast is for device test costs.