October 2023
The Electronics Packaging Technology Conference (EPTC) is an international conference organized by the IEEE Singapore RS/EPS/EDS Joint Chapter and co-sponsored by the IEEE Electronics Packaging Society (EPS). Since its inauguration in 1997, EPTC has been established as a highly-reputable, international electronics packaging conference and is the IEEE EPS flagship conference in the Asia and Pacific Region.
The 25th Electronics Packaging Technology Conference (EPTC2023) will take place from 5th to 8th December 2023 in Singapore at the Grand Copthorne Waterfront Hotel. It will feature keynotes, technical sessions, invited talks, panels, workshops, exhibits, and networking activities. Topics include modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G/6G, emerging technologies, 2.5D/3D integration technologies, smart manufacturing, automation, and AI. This year marks the 25th anniversary of EPTC. The usual 3-day event will be extended to a 4-day event to celebrate the occasion.
Registration schedule
Early Bird Registration October 31, 2023
Standard Registration December 5, 2023
Title: EPS EDMS Packaging Benchmark Suite – Past, Present, and Future
Date: 25 October, 2023
Time: 3:00 pm – 4:00 pm (UTC-04:00) Eastern Time (US & Canada)
Where: Webex Platform
Presenters: Vladimir Okhmatovski, University of Manitoba; Heidi Barnes, Keysight Technologies
Moderator: Rohit Sharma
Abstract: The mission of the IEEE EPS EDMS Packaging Benchmarks Committee is to produce a Packaging Benchmark Suite that will encourage research & development by providing information about the electromagnetic, electrical, and circuit modeling and simulation problems encountered, and the state-of-the-art solution methods used when analyzing and designing electronic packages. This presentation will cover the current state of the available packaging benchmarks, technical challenges in creating real-world benchmarks, activities to encourage usage of the benchmarks, and opportunities going forward.
Bios:
Vladimir Okhmatovski is a professor with the Department of Electrical and Computer Engineering, University of Manitoba, Canada. His research interests are the fast algorithms of electromagnetics, high performance computing, modeling of interconnects, and inverse problems. He has worked extensively on computational electromagnetics projects with Sonnet, Cadence, Intel, CEMWorks, Resonant, DND Canada, and other industry and government agencies. He was a recipient of the 2017 Intel Corporate Research Council Outstanding Researcher Award, Outstanding ACES Journal Paper Award in 2007, and received various other honors.
Heidi Barnes is a Senior Application Engineer and Power Integrity Product Owner for High-Speed Digital applications in the EDA Software Solutions group of Keysight Technologies. Her recent activities include the application of electromagnetic, transient, and channel simulators to solve signal and power integrity challenges. She is the author of over 30 papers on SI and PI, technical contributor for the new IEEE-370 Standard involving interconnect S-parameter quality after fixture removal, and recipient of the DesignCon 2017 Engineer of the Year. Recently, she was elected Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Her past experience includes ATE, RF/Microwave microcircuit packaging, and aerospace instrumentation. Heidi graduated from the California Institute of Technology in 1986 with a bachelor’s degree in electrical engineering. She has been with Keysight EDA Software since 2012.
Title: Photonic Wire Bond Packaging for Silicon Photonic Optical Fibres and Laser Integration (remote/no registration fee)
Date: 19 October, 2023
Time: 12:00 pm PDT
Register here https://events.vtools.ieee.org/event/register/372682
Title: Workshop on Quantum Computing: Devices, Cryogenic Electronics and Packaging (Hybrid event)
Date: 24-25 October, 2023
Time: 12:00 pm PDT
Location: SEMI World Hdqtrs, Milpitas, CA USA and via Webex
More information and registration https://attend.ieee.org/qc-dcep/
Title: A Macro-To-Nano Zoom Through a Real-World Battery With X-Ray Vision (remote/no registration fee)
Date: 26 October, 2023
Time: 11:50 am PDT
Register here https://events.vtools.ieee.org/event/register/366159
Title: Development and Challenges for Li-Ion Batteries for EV Applications (remote/no registration fee)
Date: 7 December, 2023
Time: 11:50AM PST
Register here https://events.vtools.ieee.org/event/register/366160
Title: Stretchable Electronics by Soft Packaging Techniques
Date: 8 November, 2023
Time: 11:00 am - 12:00 pm (UTC-05:00) Eastern Time (US & Canada)
Presenter: Dr. Yue Gu, Postdoctoral associate, Department of Neurosurgery, Yale University
Moderator: Yang Liu, Nokia Bell Labs
Abstract: Soft electronic devices are becoming increasingly important for both consumer electronics and healthcare applications. By utilizing advanced microfabrication techniques, electronic packaging, and materials design, it is possible to create functional systems that can integrate seamlessly with the human body. These devices have a low mechanical modulus, which allows them to make intimate and unobstructed contact with biological surfaces, enhancing the tissue-device coupling efficiency, thus improved bio-sensing signal qualities. In this presentation, I will discuss a primary method used to engineer soft electronic devices, including the use of intrinsically soft materials and geometrically structural designs.
Reliability, Failure Modes and Testing for Integration of Electronics and Photonics (SiPho)
16 - 17 November, 2023
SEMI Headquarters, Milpitas, CA USA
REPP 2023 is planned as a hybrid event, with both in-person and virtual participation via WebEx
Welcome to the fourth year of this new Symposium from the IEEE Electronics Packaging Society. This major Silicon Valley symposium will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging in the context of heterogeneous integration. This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses.
The intent is to bring together electrical, reliability, materials, mechanical, and computer engineers and applied scientists to address the state-of-the-art in all the interconnected fields of electronic and photonic packaging, with an emphasis on various reliability-related aspects: design-for-reliability, manufacturing, reliability modeling and accelerated testing.
Information and to register: https://attend.ieee.org/repp/
Title: Keep It Cool
Date: 14 November, 2023
Time: 08:30 - 15:30 IST (UTC +2)
Location: Tech & Talk, MATAM, Haifa, Israel
Key Speakers: Dr. Shye Shapira, CEO Phononics/Technion/Cambridge University; Prof. Ellam Yalon, Technion
Sujit Ramachandra
Abstract—The rapid emergence of a multitude of machine learning (ML) models with trillions of parameters has highlighted the need for high performance compute systems leveraging Artificial Intelligence (AI) accelerators with disaggregated memory. Considering the demanding bandwidth, density, energy and latency requirements, Silicon photonics is the technology of choice to realize these architectures. Scalable solutions can only be implemented by developing novel and reliable packaging schemes, with emphasis on thermal budgeting, reduced parasitics, and increased bandwidth density. This article covers some challenges seen when packaging photonic circuits for AI/ML systems and some innovative solutions that have been developed in the field.
I. INTRODUCTION
With the advent of GPT-4 The rapidly growing size and complexity of Machine learning (ML) and Artificial Intelligence (AI) models has crossed the trillion-mark w.r.t parameters involved [1]. The turn of the decade has seen a large number of ML machine learning models made public, each with billions of parameters. Fig. 1 shows the exponential trend of number of parameters in published ML models over the last five decades. This exponentially growing number of parameters also brings in the need for parallelization of data over tens of thousands of memory and processor nodes. Each of these nodes requires ultra-low latency and power to meet standards, Tb/s optical I/Os and high-speed interconnects between the multiple processing units involved. For instance, early publications report NVIDIA DGX systems consisting of 8 H100 GPUs, designed with a 7.2 Tb/s off chip bandwidth [2].
How Can Photonics Enable the Bandwidth Densities with Lower Energy per Bit in Emerging SIP?
Amr S. Helmy
During the 73rd ECTC event, the President's panel directed its attention towards a pivotal inquiry: "How can Photonics Enable Bandwidth Densities with Lower Energy per Bit in Emerging SIP?" The panel engaged in an extensive discussion, delving into the tools, technologies, and notably, photonics-based approaches that hold the potential to elevate the industry's interconnection bandwidth density in System-in-Package (SiP) configurations. Within this discourse, the panel addressed some of the most formidable impediments to widespread adoption, including the challenge of achieving energy-efficient performance per bit that aligns with the industry's roadmaps and established standards for both package-level and on-chip interconnection protocols.
On June 20th of this year, the IEEE EPS Vietnam chapter was established, marking a significant accomplishment that was the result of a long-standing vision. The EPS Malaysia chapter provided generous support and Dr. ANDREW TAY for this achievement. The core team of the IEEE EPS Vietnam chapter includes tech leaders from Intel and Onsemi, with Mike Fadreguilan from Intel Products Vietnam Co., Ltd.
In an impressive display of engagement, less than two months after the chapter's inception, the first IEEE EPS Vietnam chapter Tech Day event was held in successful collaboration with the EPS Malaysia chapter executive team 25th of August 2023. The event saw participation from 11 Onsemi staff and engineers, and 3 academia professors on-site, while more than 200 Intel employees joined in, and with the presence of Kenneth Tse Intel Vice President making this an unforgettable and historic occasion.
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