Email: andrew_tay@ieee.org

Topics: Thermomechanical reliability of microelectronics packages; Thermal and failure analysis of microelectronic devices; Thermal management of electronic and EV battery systems; Solder joint reliability; Delamination and fracture; Moisture effects; Modelling and simulation.

ANDREW TAY (M1991, SM2019, F2023) is currently a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), National University of Singapore (NUS). Prior to this he was a Senior Research Fellow at the Singapore University of Technology and Design and Professor in the Department of Mechanical Engineering, NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include thermo-mechanical reliability, thermal management of electronics and EV battery systems, reliability of solar photovoltaic modules and fracture mechanics. To date he has published more than 250 technical papers, 4 book chapters, 7 keynote presentations, 11 invited presentations and 3 panel discussions.

Dr Tay was the General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997. In 2006 he was appointed the inaugural Chairman of the EPTC Board, and is currently serving as its Chairman. He has been in the Executive Committee of the IEEE Singapore RS/EPS/EDS Chapter since 2000 and was its Chairman from 2010-2011 and 2018-2019. He has been involved in the international advisory boards and program committees of many electronics packaging conferences including DTIP, ECTC, EMAP, EPTC, EuroSimE, HDP, ICEPT, IEMT, IMPACT, InterPack, ITHERM and THERMINIC.

He was an Associate Editor of the ASME Journal of Electronic Packaging, an editorial board member of several journals including Microelectronics Journal and Finite Elements in Analysis and Design, and a guest editor of special issues of Microelectronics Reliability Journal, and Journal of Electronics Packaging. He is currently Co-Editor-in-Chief, Encyclopedia of Packaging Materials, Processes, and Mechanics.

He was a member of the EPS Education Committee from 1998 to 2007, and the coordinator of the Singapore Economic Development Board’s Specialized Manpower Program in Electronics Packaging and Wafer Fabrication in NUS. He has been awarded competitive research grants exceeding $14 Million for electronics packaging projects.

He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE EPS Exceptional Technical Achievement Award, the 2012 IEEE EPS Regional Contributions Award, the 2004 ASME Electronics & Photonics Packaging Division Engineering Mechanics Award, the 2000 IEEE Third Millennium Medal and the 2000 Special Presidential Recognition Award.

Email: mpoliks@binghamton.edu

Topics: Materials and Processes, Advanced Manufacturing, Flexible Hybrid Electronics, High Speed and Additive

MARK POLIKS (M: 2004) is Empire Innovation Professor of Engineering, Professor of Systems Science and Industrial Engineering, Professor of Materials Science and Engineering and Director of the Center for Advanced Microelectronics Manufacturing (CAMM) at the State University of New York at Binghamton.  In 2006 he established the first research center (CAMM), to explore the application of roll-to-roll processing methods to flexible electronics and displays, with equipment funding from the United States Display Consortium (USDC) and the Army Research Lab.  His research is in the areas of industry relevant topics that include: high performance electronics packaging, flexible hybrid electronics, medical and industrial sensors, materials, processing, aerosol jet printing, roll-to-roll manufacturing, in-line quality control and reliability.  He has received more than $20M in research funding from Federal, New York State and corporate sources and more than $30M in equipment funding from federal and state sources.  He is the recipient of the SUNY Chancellor’s Award for Excellence in Research.  He leads the New York State Node of the DoD NextFlex Manufacturing USA and was named a 2017 NextFlex Fellow.  He has authored more than one-hundred technical papers and holds forty-six US patents.  Previously he held senior technical management positions at IBM Microelectronics and Endicott Interconnect.  Poliks is a member of technical councils for the FlexTech Alliance, NBMC and NextFlex, and on the NextFlex Governing Council.  He is an active member of the IEEE Electronics Packaging Society Electronic Component and Technology Conference and served and the 69th ECTC General Chair.   Poliks received dual undergraduate degrees, with honors, in chemistry and mathematics from the University of Massachusetts and a Ph.D. from the University of Connecticut in materials science and engineering.  He was a McDonnell-Douglas post-doctoral fellow working on solid-state magnetic resonance at Washington University, St. Louis before starting his career at IBM.

Email: p.wesling@ieee.org

Topics: Origins of Silicon Valley and the Electronics Packaging Society; the IEEE/SEMI/ASME Heterogeneous Integration Roadmap and how to use it (as editor for the 2019 Roadmap).

Past IEEE SF Bay Area Communications Director and Webmaster, and Life Fellow and Distinguished Lecturer of the IEEE

Paul Wesling received his BS in electrical engineering and his MS in materials science from Stanford University.  Following assignments at GTE/Lenkurt Electric, ISS/Sperry-Univac, Datapoint Peripheral Products (VP - Product Integrity), and Amdahl (mainframe testing), he joined Tandem Computers in Cupertino (now part of Hewlett Packard) in 1985.  He designed several multi-chip module prototypes, did thermal modeling and testing, managed Tandem's Distinguished Lectures series, and organized a number of advanced technology courses for his Division and also for the IEEE.  He managed a grant from the National Science Foundation for the development of electronics packaging multimedia educational modules.  Paul retired from HP in 2001, and then served for 10 years as the Communications Director for the IEEE’s S.F. Bay Area Council and editor of the e-GRID, where he was known as “Mr. IEEE”.  He has observed the Silicon Valley for decades as an engineer, executive, resident, and educator.  He gives his IEEE DL lectures at universities, conferences and meetings around the world on the origins of Silicon Valley and its lessons for other tech hubs.

As vice president of publications from 1985 through 2008, he supervised four archival journals and a newsletter for IEEE’s Electronics Packaging Society (EPS).  He is a Fellow of the IEEE, and received the IEEE Centennial Medal, the Board's Distinguished Service award, the Society Contribution Award, the IEEE's Third Millennium Medal, and the Society President’s Recognition Award.  He has organized over 500 courses for the local IEEE chapter in the Santa Clara Valley (Silicon Valley), many of them held at Stanford University (and, more recently, at Silicon Valley company facilities).  An Eagle Scout, he served as scoutmaster of his local Boy Scout Troop for 15 years, was Advisor of a High-Adventure Crew, and enjoys backpacking, fly fishing, guitar and amateur radio (call sign: KM6LH). 

Email: ravi.v.mahajan@intel.com

Topics: Advanced Packaging Architectures, Assembly Processes and Thermal Management 

RAVI MAHAJAN is an Intel Fellow and the Director of Pathfinding for Assembly and Packaging technologies for 7-nanometer (7nm) silicon and beyond in the Technology and Manufacturing Group at Intel Corporation. He is responsible for planning and carrying out multi-chip package pathfinding programs for the latest Intel process technologies. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives.

Ravi has led efforts to define and set strategic direction for package architecture, technologies and assembly processes at Intel since joining the company’s Assembly and Test Technology Development organization in 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Earlier in his Intel career, he spent five years as group manager for thermal mechanical tools and analysis. In that role, Mahajan oversaw a Thermal-Mechanical Lab chartered with delivering detailed thermal and mechanical characterization of Intel’s packaging solutions for current and future processors.

A prolific inventor and recognized expert in microelectronics packaging technologies, Mahajan holds more than 40 patents, including the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge technology currently deployed in high volume manufacturing for FPGAs and graphics parts. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 30 papers on topics related to his area of expertise.

Ravi joined Intel in 1992 after earning a bachelor’s degree from Bombay University, a master’s degree from the University of Houston, and a Ph.D. from Lehigh University, all in mechanical engineering. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME and IEEE 2019 “Outstanding Service and Leadership to the IEEE” Award for both the Phoenix Section & IEEE Region 6. He is an IEEE EPS Distinguished Lecturer.  He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT.  Additionally he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference.  Ravi is a Fellow of two leading societies, ASME and IEEE.  He was named an Intel Fellow in 2017.