Abstract — With advancing technology nodes, conventional copper on-chip interconnects are becoming more susceptible to different scattering mechanisms such as sidewall scattering, surface roughness scattering and grain boundary scattering. These scattering mechanisms increase the per-unit-length resistance of the interconnects, thereby leading to increased signal attenuation, latency, and power losses. In order to address these limitations of conventional copper interconnects, more advanced interconnect technologies such as carbon nanotubes and hybrid copper-graphene interconnects are currently being investigated. These newer technologies exploit the enhanced electrical and material properties of novel 2D materials such as graphene to improve the overall conductive properties of the interconnects. However, in order to model the electrical properties of graphene-based interconnects, highly complicated equivalent circuit models are required, the solution of which are extremely time consuming. One approach to mitigate the high computational costs of modeling such novel interconnects is by using artificial neural network models. In this article, we review the current state-of-the-art in artificial neural networks to efficiently model the transient responses of the aforementioned emerging graphene-based interconnects.

Read more


Digital Twin has become a commonly used phrase in the context of products, processes, businesses, and more. It was first introduced in 2003 by Dr Michael Grieves, but the term was first defined in the NASA Modelling, Simulation, Information Technology & Processing Roadmap in 2010 (revised in 2012). Thus, the concept primarily evolved in the context of aerospace and manufacturing applications and was later embraced by many other industries such as healthcare. Among the newer technologies, it currently lies on the peak of the expectation curve according to a report by Gartner in 2018.

Read more

The EPS Technical Committees are seeking support from our student members. Any students interested in being the web administrator for one of our Technical Committees please contact the EPS Office

Web Administrator Role Description:

Creates website on format used by IEEE EPS Technical Committees

Keeps Technical Committee membership list up-to-date on website

Keeps Events Calendar up-to-date on website

Uploads new technical content and removes out-dated content from the website

Supports website requests from Technical Committee members.  Uses these opportunities for mentoring in interest areas of the web       administrator.

Makes suggestions in Technical Committee meetings on how to make the website more useful to the Packaging community

Monitors and reports on web site hits in Technical Committee meetings

This is an opportunity to network with professionals in the field as well as gain valuable insight into the Society's activities and focus areas. We look forward to hearing from you!

You can find the most accessed T-CPMT articles on Xplore here