June 2023
You are invited to join us for an IEEE virtual volunteer panel hosted by IEEE on Wednesday, 21 June, 2023 at 2:00-3:00pm ET.
Our panelists of IEEE members engaged with the semiconductor industry will discuss opportunities for IEEE to engage with global CHIPS initiatives. The conversation will be moderated by IEEE President-Elect Tom Coughlin. Our panel of volunteers will discuss potential opportunities, and we will invite any interested members to offer their thoughts on the discussion via the chat as well.
Please note that this invitation is exclusively for IEEE members.
As part of this event, we will be asking panelists the following questions:
-
What opportunities are there for IEEE related to CHIPS? What should we be doing globally? Regionally?
-
Are there revenue opportunities for IEEE?
-
How can we create opportunities to build a more diverse engineering workforce and create more economic opportunities in communities that are often overlooked?
-
What opportunities do we have for cross-OU collaboration?
-
Are there non-IEEE entities that we should consider partnering with in this work?
-
How can IEEE have a positive impact on CHIPS initiatives globally? How do we engage here in the spirit of our mission to advance technology for humanity?
You can RSVP here.
As this session has been rescheduled, please note that you will need to register again for the new date, even if you registered previously.
Title: Advanced Packaging for Wide Bandgap Semiconductor Power Modules
Date: 30 June, 2023
Time: 12:00pm - 1:00pm ET
Presenter: Giovanni A. Salvatore, University of Venice Ca Foscari, Italy
Bio: Dr. Giovanni A. Salvatore is an Assistant Professor at University of Venice Ca Foscari since July 2021. He got his bachelor in Electronics and Master in Micro&Nanotechnology from the Polytechnic of Turin in 2004 and 2006, respectively. He received the PhD in 2011 from EPFL for his research on ferroelectric transistors for memory and switch application.
Abstract: WBG semiconductors (i.e. SiC and GaN) outperform silicon in terms of breakdown field (x10 in case of SiC) and thermal conductivity (x2 in case of SiC), hence, ensuring smaller conduction losses and better heat dissipation combined with faster switching frequency.
Co-hosted by the IEEE Electronics Packaging Society (EPS) and the SEMI Americas Advanced Packaging Committee
Date: Wednesday, July 12, 2023
Time: 2:00-4:30 p.m. PST
Location: TechTalk Stage, Moscone South
Heterogeneous Integration through advanced packaging innovations is widely acknowledged as being increasingly important to drive performance, system availability, power efficiency, cost and time to market of microelectronics systems, from HPC & Data Centers, to 5G & Beyond, mobile, automotive, IoT, medical and health markets.
As the full microelectronics design and manufacturing supply chain come together to respond to challenges and develop new solutions, two integration technologies, in particular, are paving the way to make these innovations possible – System in Package (SiP) and Chiplets Integration. HPC systems have adopted the mantra of co-design at the system-level to address waning performance gains from shrinking transistors. By co-designing in a system-application approach, innovators across the whole ecosystem will deliver the next extension of Moore’s law in the next decade and more years.
This Heterogeneous Integration session takes a full ecosystem approach to look at how advanced packaging in SiP and Chiplets are paving the way for the Future of HPC and Hyperscale computing.
The EPEPS 2023 call for papers is out!
The 32nd IEEE Conference on Electrical Performance of Electronic Packaging and Systems will be held on October 15-18, 2023 in Milpitas, CA.
Milpitas will welcome attendees in the heart of the Silicon Valley, within short distance of many prominent microelectronic companies, and of the San Jose and San Francisco international airports.
You are invited to submit papers in PDF format, up to three pages long. Submit papers online by July 17, 2023, at:
http://www.epeps.org/submission.html
Accepted papers will be published on IEEEXplore. Selected papers will be invited for a special issue in IEEE Transactions on Components, Packaging, and Manufacturing Technology. Full details can be found on the Call for Papers:
Jie Geng, Ph.D. and Hongwen Zhang, Ph.D.
Indium Corporation
Clinton, NY 13413
e-mail: jgeng@indium.com
I. INTRODUCTION
Lead-free solder alloys have been widely adopted by the electronics industry since the Restrictions on Hazardous Substances (RoHS) regulations were implemented in the European Union in July 2006. In the past decades, lead-free SnAgCu (“SAC”) solder alloys such as Sn3.0Ag0.5Cu (SAC305) and Sn3.8Ag0.7Cu (SAC387) have been used extensively in portable, computing, and mobile electronics, which operate in temperatures of 125°C and below. Automotive electronics must operate in temperatures around 150°C for under-the-hood devices and below 125°C for devices in the passenger compartment. These electronics must also be able to function in very low temperatures, requiring an operational range of -40°C to +150°C.
For such harsh environments, the traditional binary or ternary lead-free Sn-rich solder alloys are not reliable enough to survive. Relative to the melting temperature of most Sn-rich solders, the homologous temperature at 150°C equals to 0.876 for SnAgCu-3Bi, 0.863 for SnAgCu, 0.856 for Sn-3.5Ag and 0.846 for Sn-0.7Cu, indicating that atomic diffusion will facilitate microstructural evolution and accelerate joint degradation.
3D PEIM Conference Reveals the Five “M”s in Power Electronics
Multiscale, Multiphysics, Modeling, Materials and Manufacturing
M Raj Pulugurtha (Florida International University), Brian Narveson (Narveson Innovative Consulting),
John Bultitude (KEMET, A Yageo Company) and Vanessa Smet (Georgia Institute of Technology)
The 3D Power Electronics Integration and Manufacturing (3D PEIM 2023) conference highlighted the need for multiscale multiphysics modeling to design for advanced topologies and architectures, coupled with innovations in materials and manufacturing to reliability for emerging computing, communication and automotive markets. This article points to selected key fundamental technology take-home lessons from the 3D PEIM conference held in FIU, Miami in February 2023.
The 3D Power Electronics Integration and Manufacturing Symposium, chaired by Markondeya Raj Pulugurtha, FIU was held from February 1-3, 2023 and hosted by Florida International University (FIU), in Miami, Florida. The Symposium is financially sponsored by Power Source and Manufacturing Association (PSMA) and technically sponsored by the IEEE Electronic Packaging Society (EPS) and Florida International University. The sponsor Chair, Devarajan Balaraman (Wolfspeed) engaged with seven Partner/Exhibitors: Amkor Technology, FIU Biomedical Engineering, KEMET a YAGEO Company, Wolfspeed, Indium Corp and Carbice, who also contributed to the success of the event. The workshop technical program was led by technical co-Chairman John Bultitude, KEMET, A Yageo Company, and Vanessa Smet, Georgia Tech. The Symposium focused on multiscale power electronics and addressing its key challenges through Multiphysics modeling coupled with emerging topologies and architectures, materials, integration and manufacturing to create state of the are power systems
The IEEE International 3D Systems Integration Conference (3DIC) 2023 was held at Tyndall National Institute, University College Cork, Ireland from May 10th -12th, 2023. This conference combines the previous IEEE EDS Society sponsored International 3D System Integration Conference, held in Tokyo in 2007 & 2008, and the Fraunhofer and IEEE CPMT sponsored International 3D System Integration Workshop held in 2003 & 2007 in Munich. After the first combined conference in San Francisco 2009, the 3DIC took place in Munich in 2010 followed by Tokyo in 2011. The intention was to rotate over the three continents: America, Europe and Asia. 2023 was again Europe´s turn and we were very happy that Tyndall National Institute hosted this year´s conference in the beautiful city of Cork, Ireland.
The distinguished lecture was presented by Dr. John Hon Shing Lau with the topic of "Chiplet Design and Heterogeneous Integration Packaging" at Tsinghua University, May 11. The lecture was hosted by EPS Beijing Chapter.
Dr. Lau introduced the main driving forces of the rapid development of Chiplet. He expressed that, the feature size that a monolithic SoC can use has been limited by technology and cost factors at present, and it has become increasingly difficult to continue scaling in accordance with Moore's Law. Meanwhile, cost can be significantly reduced because the manufacturing yield improves as die size gets smaller. As a result, Chiplet is becoming an emerging solution that has gained widespread attention.
You can find the most accessed T-CPMT articles on Xplore here.