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The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

·       Outstanding Sustained Technical Contribution Award

·       Electronics Manufacturing Technology Award

·       William Chen Distinguished Service Award

·       Exceptional Technical Achievment Award

·       Outstanding Young Engineer Award

·       Regional Contributions Award


The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Awards Nomination Form

PhD Fellowship Nomination Form 

Nomination Period September 15, 2023 - January 21, 2024

The 2024 IEEE EPS membership certificates are now available.

EPS Membership Cert 2024











Steps to download and print your certificate:

 Log into IEEE Collabratec at ieeecollabratec.org

Click on your name in the top right of the screen and select “IEEE Membership Certificates”.

From the “Member Certificates” page select your certificate to download the PDF.

Open the PDF and print.

The EPS proudly congratulates the lastest recipient of the IEEE Certificatate of Achievement:

Vance Liu, Micron Memory Technology

Due to the current situation in Israel,  the IEEE COMCAS 2023 conference, originally scheduled for November 6-8, 2023 in Tel Aviv, will be postponed to July 9 - 11, 2024.

The conference organizers are carefully evaluating all aspects of this postponement. All further related information will be announced as soon as possible on the EPS conference website.

Przemyslaw Gromala 1, Adwait Inamdar 2, Willem van Driel 2, GuoQi Zhang 2, Christopher Bailey 3, Luu Nguyen 4, Benson Chan 5,     Jong Eun Ryu 6, Farnood Rezaie 7, Abram Detosky 8


1 Robert Bosch GmbH, Reutlingen, Germany; 2 Delft University of Technology, Delft, Netherlands; 3 Arizona State University, Tempe, Arizona, USA; 4 PsiQuantum, Palo Alto, California, USA; 5 Binghamton University, New York, USA; 6 North Carolina State University, Raleigh, NC, USA; 7 Cisco Systems Inc., San Jose, California, USA; 8 Intel Corporation, Hillsboro, Oregon, USA



Digital Twins (DT) have become a groundbreaking concept in the field of electronics packaging and electronic systems. In an era characterized by rapid technological advances and increasing complexity in electronics packaging products, digital twins offer a revolutionary approach.

These virtual replicas of physical semiconductor circuits, electronic devices, or systems provide engineers and researchers with invaluable information, enabling real-time monitoring, analysis and optimization. This innovative technology not only improves product development and performance, but also significantly streamlines design and manufacturing processes, ultimately pushing the boundaries of what is possible in the world of electronics packaging and electronics enabled systems.

However, it’s worth noting that the concept of digital twins can sometimes vary depending on the context, application field, and one’s expertise or experience. In this article, we aim to explore the diverse applications of digital twins in the electronics industry, starting with an examination of various existing definitions.

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  Aditya Vaidya                                    Yinglei Ren 

   Intel Corporation                                Intel Corporation

                                  aditya.s.vaidya@intel.com                  yinglei.re@intel.com                               


The world is becoming increasingly impatient and demanding. There is need for fast internet, social media pages to load quickly, and have in-person feeling with colleagues while working from home. On a serious note, processing large amounts of data in the shortest amount of time has become the norm in a world dominated by artificial intelligence (AI), machine learning and large amounts of data in general. A direct consequence of this is on the bandwidth (BW) requirements for different communication protocols to and from a microprocessor. In recent years, the signaling speed for standard protocols like Memory and Peripheral Component Interconnect Express (PCIe) have been increasing at an exponential rate to get higher BW as shown in Figure 1 below [1,2].

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Title: Reliability and lifetime estimation of power electronic modules under high temperature loading conditions

Date: December 12, 2023

Time: 1:00 pm EST

Presenter: Paul Paret

Abstract: Advanced packaging technologies are currently being designed and developed by the power electronics industry however, the maximum operating temperature is still limited to 175°C for the silicon carbide devices. Bonded materials such as sintered silver, sintered copper, and polymeric materials are potential candidates for high temperature operation, but it is critical to characterize and evaluate its reliability under harsh operating conditions. In the first part of this webinar, the accelerated experiments and thermomechanical modeling results of these bonded materials, and their lifetime prediction models developed at the National Renewable Energy Laboratory (NREL) are discussed.

Bio: Paul Paret is a researcher in the Center for Integrated Mobility Sciences at the National Renewable Energy Laboratory. In this role, Paul leads the computational modeling efforts to simulate the thermal and thermomechanical behavior and develop lifetime prediction models of various bonded materials in power electronics packages used in electric-drive vehicles and aviation systems.


Register Here

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Title: Nanopackaging for AI and power delivery 

Date: December 13, 2023 

Time: 11AM EST (8AM PST) 

Speakers: Dr. Siddharth Ravichandran and Prof. Kuan-Neng Chen  

Moderator: Dr. Srikrishna Sitaraman  

Abstract: The proliferation of artificial intelligence (AI) applications has increased the demand for compute performance and memory capacity. This is happening at a time when the semiconductor industry is facing challenges associated with the slowing down of Moore's Law. Chiplet integration using nanopackaging is being viewed as a critical enabling technology for supporting AI applications. Such highly integrated systems require a multitude of materials to support electrical, mechanical, thermal, and chemical properties. In addition, these materials need to be compatible with packaging processes to ensure compatibility with low-cost manufacturing solutions.


Register Here

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Kai Chat Tan

IEEE EPS Malaysia and IEEE Malaysia Section hosted a highly successful Advanced Packaging Workshop on two separate occasions, on the 17th of October in Bangi, and on the 19th of October in Penang, covering the southern and northern regions of Malaysia. This event, with jointly supported by IEEE Malaysia Section of Professional Activities and Industrial Relations (PAIR), attracted a substantial turnout, with over 200 participants hailing from various prominent organizations, including NXP, onsemi, Intel, Micron, ST Microelectronics, University of Malaya and more.

The workshop featured the invaluable insights and expertise of IEEE EPS distinguished lecturers, Dr. Tanja Braun and Jan Vadarman. They presented the latest advancements in packaging technology within the industry and shed light on emerging trends, particularly within the realm of automotive applications.

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You can find the most accessed T-CPMT articles on Xplore here.