EPS Distinguished Certificates
Nominations for the 2022 Distinguished Achievement Certificates will be accepted two times per year.
The first round will run from January 1 through June 30 and the second round from August 30 through October 31.
Maximizing Benefits of Adaptive Test Techniques by Integration of ML and Test Infrastructure Improvements
Abhijit Sathaye
Principal Engineer
Manufacturing and Product Engineering
Intel Corporation
Hillsboro, OR, USA
abhijit.sathaye@intel.com
Abstract:
Testing Si devices in high volume manufacturing (HVM) is getting more challenging and expensive, owing to the increasing complexity of the devices under test. Semiconductor companies are adding more capabilities on a package, transistor density is going up, end user applications are more varied than ever before.
Adaptive test techniques have been used in industry for many years now. Applications of machine learning (ML) techniques have also been demonstrated and widely used in test today.
Verifying Results of Quantum Circuit Compilation Flows
Lukas Burgholzer∗ Robert Wille∗†∗
Institute for Integrated Circuits, Johannes Kepler University Linz, Austria
†Software Competence Center Hagenberg GmbH (SCCH), Hagenberg, Austria
lukas.burgholzer@jku.at robert.wille@jku.at
https://iic.jku.at/eda/research/quantum/
Quantum computers aim to change the way we tackle certain problems in the future. Numerous quantum computing applications with a near-term perspective (e.g., for finance, chemistry, machine learning, optimization) and with a long-term perspective (i.e., cryptography, database search) are currently investigated. However, in order to realize those, a multitude of (computationally complex) design tasks have to be conducted—eventually forming a process called quantum circuit compilation. However, in order to realize those, a multitude of (computationally complex) design tasks have to be conducted—eventually forming a process called quantum circuit compilation. However, in order to realize those, a multitude of (computationally complex) design tasks have to be conducted—eventually forming a process called quantum circuit compilation. This results in descriptions of quantum algorithms at various abstraction levels which may significantly differ in their basis operations and structure.
3D Integration Technologies for Various Quantum Computing Devices
Peng Zhao1,2 , Yu Dian Lim1 , Hong Yu Li2 , Guidoni Luca3 , and Chuan Seng Tan1,*
1Nanyang Technological University, Singapore
2A*STAR Institute of Microelectronics, Singapore 3Université de Paris, France
*Email: tancs@ntu.edu.sg
INTRODUCTION
With the slowdown of transistor node scaling in the past decade, advanced three-dimensional (3D) integration technologies have been developed as an alternative approach for the continuity of Moore’s law, specifically in reducing form factor, cost, power and increasing performance. By extending the conventional two-dimensional layouts, assembly, and interconnections into the third dimension, 3D integration has progressively become the primary building block of advanced electronic devices.
By extending the conventionally two-dimensional layouts, assembly, and interconnections into the third dimension, 3D integration has progressively become the primary building block of advanced electronic devices.
EPS Chapter Awarded 2021 Region 6 Outstanding Chapter of the Year
Congratulations to the EPS Santa Clara Valley / Oakland East Bay/San Francisco Chapter, which was named “2021 Region 6 Outstanding Chapter of the Year” (selected from among Society Chapters and Technical Councils but not Affinity Groups).
The award plaque will be presented at the 2022 Region 6 Op Com meeting that will be held in Phoenix, AZ in late January.