September 2022
Election Principles
The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.
Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG. The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.). There is no election of a Young Professional this year.
The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.
EPS Major Awards
A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:
· Outstanding Sustained Technical Contribution Award
· Electronics Manufacturing Technology Award
· William Chen Distinguished Service Award
· Exceptional Technical Achievement Award
· Outstanding Young Engineer Award
· Regional Contributions Award
The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.
PhD Fellowship Nomination Form
Nomination Period September 15, 2022 - January 21, 2023
Round 2 of the EPS Distinguished Achievement Certificates nomination period is now open.
Applications for these certificates will be accepted until October 31, 2022:
Distinguished Achievement Certificate for Professional Engagement and Service
Distinguished Achievement Certificate for Technical Leadership and Expertise
Beginning with the 2023 renewal cycle, EPS members will have access to the new EPS Digital Library!
This will include online access via Xplore to the Transactions on Components, Packaging and Manufacturing Technology (T-CPMT), EPS sponsored conference proceedings including ECTC, ESTC, ITherm and more!
Unlimited access to current and past issues of T-CPMT and proceedings for EPS sponsored conferences from current year to the early nineties.
IEEE ICSJ 2022 will be held at Kyoto, Japan from November 9 -11th, 2022.
ICSJ is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. This conference was inaugurated in 1992 as "The VLSI Packaging Workshop in Japan (VPWJ)" to provide a platform for you to communicate and interact with global leaders in packaging technology. Later in 2010, this conference was renamed to "ICSJ" and ICSJ2022 is the 11th. ICSJ meeting, or 20th. conference since establishing VPWJ. Even still vague situation with COVID19, following the last year, ICSJ2022 will be a hybrid event of on-site and virtual meetings where several presentation options are available for the authors to select and the details will be announced on the official website at a later date.
The symposium tries to forecast where the packaging technology is heading. In 2022, our focus is on key electronics packaging technologies for the next-generation mobile networks and their applications for sustainable well-being for people and society, and emphasises on the following main topics: Photonics, Advanced Packaging, Process & Material, Power & Automotive Electronics, Bioelectronics & Healthcare, and Signal/Power Integrity.
Submit your abstract for the 73rd ECTC!
The premier international packaging, components, and microelectronics systems technology conference
You are invited to submit an abstract proposal about new developments and technology related to the following:
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Submission Guidelines
The content must be original, previously unpublished, non-confidential and without commercial content.
All abstracts and proposals must be submitted electronically at our website by 10 October 2022. Get more details here. Selected authors and instructors will be announced by 12 December 2022. The first 100 people to submit abstracts will be entered into a drawing to win a free ECTC 2023 registration.
The opportunity to access Best Papers from ECTC 2021 as Open Access ends September 24th, 2022.
1) Best Session Paper
Proof of Concept: Glass-Membrane Based Differential Pressure Sensor
Anatoly Glukhovskoy - Leibniz University, Maren S. Prediger - Leibniz University, Jennifer Schäfer- Leibniz University, Norbert Ambrosius - LPKF Laser & Electronics AG, Aaron Vogt - LPKF Laser & Electronics AG, Rafael Santos - LPKF Laser & Electronics AG, Roman Ostholt - LPKF Laser & Electronics AG, and Marc Christopher Wurz - Leibniz University
2) Best Interactive Presentation Paper
System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
Arnaud Garnier, Laetitia Castagné, Florent Gréco, Thomas Guillemet, Laurent Maréchal, Mehdy Neffati, Rémi Franiatte, Perceval Coudrain, Stéphane Piotrowicz, and Gilles Simon - CEA-Leti. Authors 1-3, 7, 8, 10: CEA-Leti, Author 4: Thales DMS, Authros 5, 6: United Monolithic
Arnaud Garnier - CEA-Leti, Laetitia Castagné - CEA-Leti, Florent Gréco - CEA-Leti, Thomas Guillemet - Thales DMS, Laurent Maréchal - United Monolithic Semiconductors, Mehdy Neffati - United Monolithic Semiconductors, Rémi Franiatte - CEA-Leti, Perceval Coudrain - CEA-Leti, Stéphane Piotrowicz - III-V Lab, Gilles Simon - CEA-Leti
3) Outstanding Session Paper
Ultra-Thinning of 20 nm-Node DRAMs down to 3 um for Wafer-on-Wafer (WOW) Applications
Zhiwen Chen - Tokyo Institute of Technology, Naoko Araki - Tokyo Institute of Technology, Youngsuk Kim - Tokyo Institute of Technology, Tadashi Fukuda - Tokyo Institute of Technology, Koji Sakui - Tokyo Institute of Technology, Tomoji Nakamura - Tokyo Institute of Technology, Tatsuji Kobayashi - Micron Memory Japan, Takashi Obara - Micron Memory Japan, and Takayuki Ohba - Tokyo Institute of Technology
4) Outstanding Interactive Presentation Paper
Cu Recrystallization and the Formation of Epitaxial and Non-Epitaxial Cu/Cu/Cu Interfaces in Stacked Blind Micro Via Structures
T. Bernhard, S. Dieter, R. Massey, S. Kempa, E. Steinhäuser, F. Brüning. All authors: Atotech Deutschland GmbH.
5) Intel Best Student Session Paper
Mechanical Behavior and Reliability of SAC+Bi Lead Free Solders with Various Levels of Bismuth
KM Rafidh Hassan, Jing Wu, Mohammad S. Alam, Jeffrey Suhling, and Pradeep Lall. All authors: Auburn University
Adoption of advanced packaging methods, such as 2.5D and chiplet based MCM assembly, combined with higher speed I/O, increasing I/O counts, and increasing product complexity have resulted in significant growth to FCBGA substrate size and complexity, which has strained the industry FCBGA substrate supply the last few years. Significant application drivers for increasing substrate complexity have been high performance computing (HPC, including server CPUs and AI accelerators), 5G base stations, and high-end networking. Substrate complexity requirements have increased with higher layer counts, reduced chip and package interconnect pitch, finer substrate line and space wiring, increased stacked via counts, higher package I/O requirements, and custom requirements such as embedded bridge diei or passive components.
I. INTRODUCTION
There are two problems in the enlargement of the High-performance CPU/ASIC package. One is the power consumption increasing of Hi-performance chips mounted on packages. Second is the assembly yield and reliability of the 2nd level connection such as BGA or LGA socket. While a large power consumption requires stable power supply to the LSI, the allowable margin decreases and becomes difficult as the clock frequency increase and the driving voltage decreases. Therefore, the low impedance of the power supply in the package substrate is one of the important issues for improving power integrity. We solved this problem by embedded thin film capacitor technique in the package substrate.
During the conference luncheon in June 2022, past general chairs of the ECTC conference gathered together for a memorial photo.
Thank you for your leadership! 
Standing left to right - Eric Perfecto '07, Mark Poliks '19, Henning Braunisch '17, Alan Huffman '16, Tom Reynolds '00,
Chris Bower '20, Torsten Wipiejewski '08,Patrick Thompson '06, Wolfgang Sauter '13 - '14
Sitting left to right - Dave McCann '12, Nancy Stoffel '21, Beth Keser '15, Rao Bonda '09